作者:
FUJIWARA, ETANAKA, TMemberFaculty of Engineering
Tokyo Institute of Technology Tokyo Japan 152 Eui Fujiwara:received his B.S. and M.S. degrees in Electronics Engineering in 1968 and 1970
respectively and his Dr. of Eng. degree in 1981 all from Tokyo Institute of Technology. In 1970 he joined the NTT Musashino Electrical Communication Laboratories and engaged in developing PIPS-1 and PIPS-11 computer systems. In 1988 he joined the Department of Computer Science Tokyo Institute of Technology as an Associate Professor. In 1990 he became a full Professor. He was a Visiting Professor at the Center for Advanced Computer Studies the University of Southwestern Louisiana from June 1985 to July 1986. His current research interests include coding theory for computers fault-tolerant memories VLSI defect-toleranceand WSI systems. He is a co-author ofError Control Coding for Computer Systems(Prentice-Hall1989) EssentiaLF of Error-Correcting Coding Techniques (Academic Press 1990) and other books. Dr. Fujiwara received the Young Engineer Award from the I.E.I.C.E. in 1978 and the Teshima Memorial Research Award in 1991. He is a senior member of the IEEE and a member of the Information Processing Society Japan. Associate Member
Because of its capability of high-speed search, the associative memory (CAM) is expected to be used in a variety of information processing systems. In this paper, novel fault-tolerant techniques which are effective fo...
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Because of its capability of high-speed search, the associative memory (CAM) is expected to be used in a variety of information processing systems. In this paper, novel fault-tolerant techniques which are effective for on-line use are proposed for TLB which is an example of the application of CAM. First, fault and error models of the TLB consisting of the CAM part and the SRAM part are clarified. Then, the fault-tolerant techniques for these faults and errors, such as distance separable technique, cod-ing technique, simplified 1-out-of-n check and graceful degradation, are proposed. The distance separable technique which encodes the data stored in the CAM part is the one which masks the faulty CAM part and prevents errors from propagating to the subsequent circuits. The coding technique checks the one-to-one correspondence between the data in the CAM and those in SRAM by using the SEC-DED code with byte error detection capability, i.e., SEC-DED-SbED code, and at the same time it detects and corrects errors in the data stored in SRAM. The simplified 1-out-of-n check processes association errors. The graceful degradation gives a flag in the faulty memory section and prevents it from being used. The methods proposed in this paper are evaluated from area augmentation and error detection capability perspectives. The results show that the fault-tolerant TLB with 32 virtual address bits, 32 physical address bits and 128 entries gives single fault detection probability of nearly 99 percent with 28 percent area increase.
In this article a multimedia computer-assisted learning (MCAL) system is presented. The major objective of this work was to investigate the potential of using such systems as tools for transferring instructional cours...
In this article a multimedia computer-assisted learning (MCAL) system is presented. The major objective of this work was to investigate the potential of using such systems as tools for transferring instructional course information through various types of computer media as opposed to the classic CAL systems. The philosophy and techniques employed to design the system are investigated. Usage of the implemented system and its merits have been illustrated through its application to teach engineering students and technicians the theory and concepts of marine radar. System design, implementation, test, and revision phases are presented and discussed.
作者:
Chiodo, E.Menniti, D.Testa, A.Picardi, C.Elio Chiodo (1959) received the degree in Electronics Engineering in 1985
and the Ph.D. degree in Computational Statistics both from the University of Naplefltaly. He is a Researcher at the Department of Electrical Engineering of the University of Naples and a member of the Italian Statistical Society. His areas of interest include probabilistic methods applied to electric power systems analysis. (University of Naples Fedrrico 11. Electrical Engineering Dept.via Claudio 21 1-80125 Naplefltaly T +3981/7683226 Fax+3981/2396897) Daniele Menniti (1958) received the degree in Electrical Engineering from the University of Calabria. Cosenzataly and the Ph.D. degree in Electrical Engineering from the University of NapleslItaly
in 1984 and 1989 respectively. He is a researcher at the Electronic. Computer and Systems Science Department of the University of Calabria. Italy. Hiscurrent research interests concern electric power system analysis real-time control and automation. (University of Calabria Electronic Computer and Systems Science Dep. Arcavacataji Rende (CS). 1-87036 CosenzdItaly T +39984/494707. Fax +39984/4947 13) Alfredo Testa (1950) received the degree in Electrical Engineering from the University of Naples/Italy
in 1975. He is an Associate Professor in Electrical Power Systems at the Department of Electrical Engineering of the University of Naples. He is engaged in researches on electrical power systems reliability and harmonic analysis. (University of Naples Federico 11. Electrical Engineering Dep. via Claudio '2 1 1-80 I25 NapleslItaly T + 39 8 I/7 68 3'2 11. Fax+3981/2396897) Ciro Picardi (1949) received the degree in Electronics Engineering from the University of Naples/Italy
in 1975. He is currently Associate Professor in Process Control at the Department of Electronic Computer and System Science of the University of Calabria. Italy. His current research interests are in the area of electrical drives robotics neural networks and fuzzy control. (University of Calabria Electronic. Compu
An artificial‐neural‐network (ANN) application for steady‐state security evaluation of electrical power systems is presented. Such application is based upon a combined use of a multilayer back‐propagation neural n...
An integrated sequence of ex-situ wet-chemistry, and on-line low-temperature remote plasma-assisted techniques, for fabricating device-quality Si/SiO2 interfaces on Si(111) wafers is reported. Three factors contribute...
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An integrated sequence of ex-situ wet-chemistry, and on-line low-temperature remote plasma-assisted techniques, for fabricating device-quality Si/SiO2 interfaces on Si(111) wafers is reported. Three factors contribute to the device quality interfaces i) the orientation of the Si surface relative to a perfect (111) alignment, ii) the pH of the final HF/NH4F rinse used in the pre-deposition wet-chemistry processing, and iii) the specific plasma-assisted oxidation and deposition processes used to form the SiO2/Si heterostructure.
We discuss a novel approach to the formation of deposited stacked-gate structures that combines several different processing steps into a single chamber with multi-function oxidation, passivation and deposition capabi...
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We discuss a novel approach to the formation of deposited stacked-gate structures that combines several different processing steps into a single chamber with multi-function oxidation, passivation and deposition capabilities. To form a Si-based stacked gate structures the following in-situ steps can be performed i) a final cleaning/passivation of the Si surface, ii) formation of the SiO2/Si interface, iii) deposition of a single, or multi-layer dielectric, e.g., SiO2, or an oxide/nitride/oxide (ONO) structure, and iv) deposition of a polysilicon gate electrode. We discuss the fabrication and performance of test device structures that combine remote plasma and rapid thermal processing steps, but omit the polysilicon deposition, and use an Al gate electrode instead. These structures are use to demonstrate the effectiveness of different interface formation processes.
An ensemble of neural networks with competitive learning and consensus schemes is proposed. Conventional learning methods utilize all the dimensions of the original input patterns. However, a particular attribute of t...
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This paper presents experimental results on empirical nonlinear models (of the Hammerstein type) for a reactive ion etcher. A nonlinear tracking controller design based on the nonlinear model was implemented. Experime...
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This paper presents experimental results on empirical nonlinear models (of the Hammerstein type) for a reactive ion etcher. A nonlinear tracking controller design based on the nonlinear model was implemented. Experimental data on the performance of the control system is also included.
The promise of new architectures and more cost-effective miniaturization has prompted interest in hybrid molecular and semiconductor computers. Nature has already optimized some molecules for such applications. We exa...
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The promise of new architectures and more cost-effective miniaturization has prompted interest in hybrid molecular and semiconductor computers. Nature has already optimized some molecules for such applications. We examine here the use of the protein bacteriorhodopsin in associative and three-dimensional memories and the potential for making hybrid computer systems which combine semiconductor and biomolecular components.< >
This paper explores an inherent feedback limitation of using decentralized LTI control on a two-input, two-output LTI plant. The result is motivated by, and illustrated on, a reactive ion etcher.
This paper explores an inherent feedback limitation of using decentralized LTI control on a two-input, two-output LTI plant. The result is motivated by, and illustrated on, a reactive ion etcher.< >
Proposes a new competitive learning algorithm that dynamically creates output neurons. The number of output neurons is increased as learning proceeds, whereas conventional competitive learning algorithms use all of th...
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Proposes a new competitive learning algorithm that dynamically creates output neurons. The number of output neurons is increased as learning proceeds, whereas conventional competitive learning algorithms use all of the available output neurons during the entire learning phase. An acceptance test for the winning output neuron is performed using class thresholds if the number of created output neurons is less than the predefined maximum number. Accepted input vectors are used to adjust the reference vector of the winning output neuron. If an input vector is rejected, it is used as the initial reference vector of a new output neuron. The proposed method gets around the drawbacks of the conventional competitive learning algorithms by changing the class threshold values of output neurons dynamically. Experiments with remote sensing data and speech data indicate the superiority of the proposed algorithm in comparison to the conventional competitive learning methods.< >
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