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1991 IEEE Region 10 International Conference on EC3-Energy, computer, Communication and Control Systems, TENCON 1991

作者： Sundaram, S. Mohan, T.S. Patnaik, L.M. Indian Institute of Science Bangalore560 012 India Computer Aided Design Laboratory India Supercomputer Education and Research Centre Knowledge Based Computer System Laboratory India Supercomputer Education and Research Centre Dept. of Computer Science and Automation Microprocessor Applications Laboratory India

ISBN: (纸本)0780305388

Increase in the complexity of VLSI digital circuit design demands faster logic simulation techniques than those currently available. One of the ways of speeding up existing logic Simulation Agorithms is by exploiting the inherent parallelism of the sequential version. In this paper, we explore the possibility of mapping an event driven logic simulation algorithm onto a cluster of processors interconnected by an ethernet. The set of events at any simulation time. step is partitionecl by the Master Task (running on the host processor) anlong the Worker Tasks(running of the other processor's). The partitioning scheme ensures a balanced load. Each Worker Task determines the fanout, elementts, evaluates them independently and comes up with the new event list which is passed onto the Master Task. After receiving the event lists from all the workers, the Master Task increments the simulation time step, computes the new event list partition for the next simulation cycle. We have implemented this distributed logic simulation algorithm on a set of 8 VAXstations using CT - A package for distributed programming. The paper concludes with a note on the speedup figures obtained on the ISCAS benchmark circuits. © 1991 IEEE.

关键词： computer circuits

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A temporal logic over partial orders for analysis of real-time properties of distributed programs

A temporal logic over partial orders for analysis of real-ti...

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1991 IEEE Region 10 International Conference on EC3-Energy, computer, Communication and Control Systems, TENCON 1991

作者： Mall, R. Patnaik, L.M. Supercomputer Education and Research Centre Indian Institute of Science Dept. of Computer Science and Automation Bangalore560 012 India Supercomputer Education and Research Centre Indian Institute of Science Microprocessor Applications Laboratory Bangalore560 012 India

ISBN: (纸本)0780305388

Temporal logic is widely acclaimed to be a highly successful tool for analyzing non-real-time properties of programs. However, a few fundamental problems arise while designing temporal logic-based-techniques to verify real-time properties of programs. in this context, we formulate a modal logic called distribued logic (DL) by using ideas from both the interleaving and partial ordering approach. This logic uses spatial modal operators in addition to temporal operators for representing real-timed concurrency. In addition to the syntax and semantics of the logic, programming model and a formal proof technique based on the logic are also presented. Finally, use of the proof method is illustrated through the analysis of the real-time properties of a generic multiproceess producer/consumer program. © 1991 IEEE.

关键词： Temporal logic

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Fully-adaptive minimal deadlock-free packet routing in hypercubes, meshes, and other networks 91

Fully-adaptive minimal deadlock-free packet routing in hyper...

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Third Annual ACM Symposium on Parallel Algorithms and Architectures - SPAA'91

作者： Pifarre, G.D. Gravano, L. Felperin, S.A. Sanz, J.L.C. ESLAI Escuela Superior Latino Americana de Informática CC 3193 (1000) Buenos Aires Argentina. and Computer Research and Advanced Applications Group IBM Argentina Ing. E. Butti 275 (1300) Buenos Aires Argentina. and Computer Science Dept. IBM Almadeu Research Center San José California Computer Science Dept. IBM Almaden Research Center San José California. Computer Research and Advanced Applications Group IBM Argentina Ing. E. Butti 275 (1300) Buenos Aires Argentina

ISBN: (纸本)0897914384

This paper deals with the problem of packet-switched routing in parallel machines. Several new routing algorithms for different interconnection networks are presented. While the new techniques apply to a wide variety of networks, routing algorithms will be shown for the hypercube, the 2-dimensional mesh, and the shuffle-exchange. The techniques presented for hypercubes and meshes are fully-adaptive and minimal. A similar technique can be devised for tori. A fully-adaptive and minimal routing is one in which all possible minimal paths between a source and a destination are of potential use at the time a message is injected into the network. Minimal paths followed by messages ultimately depend on the local congestion encountered in each node of the network. In the shuffle-exchange network, the routing scheme also exhibits adaptivity but paths could be up to 3 log TV long for an iV node machine. The shuffle-exchange algorithm is the first adaptive and deadlock-free method that requires a small (and independent of N) number of buffers and queues in the routing nodes for that network. Furthermore, all of the new techniques are completely free of deadlock situations. In dynamic message injection models, the routing methods are also ensured to be free of livelock if messages competing for resources are handled with fairness. In contrast to other approaches in which adaptivity, deadlock and livelock freedom can be guaranteed at the expense of complex architectures, the algorithms presented in this paper require a very moderate amount of routing hardware. In particular, it will be shown that only two central queues per routing node of the network are necessary for the cases of the 2-dimensionaJ mesh and the hypercube, and four queues for the shuffle-exchange. This paper demonstrates that "hanging" an interconnection network from a node [Gun81, MS80, BGSS89, Kon90] is a convenient methodology for creating and visualizing routing functions and understanding deadlock-free polic

关键词： Interconnection networks (circuit switching)

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On using cad models to compute the pose of curved 3D objects

On using cad models to compute the pose of curved 3D objects

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1991 Workshop on Directions in Automated CAD-Based Vision, CADVIS 1991

作者： Ponce, Jean Hoogs, Anthony Kriegman, David J. Beckman Institute Dept. of Computer Science University of Illinois UrbanaIL61801 United States General Electric Aerospace Military and Data Systems Operations PhiladelphiaPA19101 United States Center for Systems Science Dept. of Electrical Engineering Yale University New HavenCT06520 United States

ISBN: (纸本)0818621478

A new approach is presented for explicitly relating image observables to models of curved three-dimensional objects. This relationship is used for object recognition and positioning. Object models consist of collections of parametric surface patches. The image observables considered are raw range data, surface normals and Gaussian curvature, raw image contours, contour orientation and curvature, raw image intensity, and intensity gradient. Elimination theory provides a method for constructing an implicit equation that relates these observables to the three-dimensional position and orientation of object models. Determining the unknown parameters is reduced to a fitting problem between the implicit equation and the observed data points. A preliminary implementation is presented. © 1991 Proceedings - Workshop on Directions in Automated CAD-Based Vision, CADVIS 1991. All rights reserved.

关键词： Object recognition

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AN ANNEALING-BASED CIRCUIT PARTITIONER FOR HYPERCUBE ARCHITECTURE: DESIGN AND PERFORMANCE EVALUATION

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International Journal of High Speed Computing 1990年第1期2卷 69-84页

作者： SRILATA RAMAN L.M. PATNAIK Dept. of Electrical and Computer Engineering and Coordinated Science Laboratory University of Illinois at Urbana-Champaign IL 61801 U.S.A Microprocessor Applications Laboratory Dept. of Computer Science and Automation and Supercomputer Education and Research Center Indian Institute of Science Bangalore 560 012 India

This paper discusses the parallel implementation of a hypercube-based circuit partitioning scheme. The circuit partitioner is based on a simulated annealing algorithm and is designed to provide near optimal circuit partitions for simulating the circuits on a hypercube architecture. The circuit partitioning scheme optimizes multiple criteria such as tight coupling of nodes within a subcircuit, load balancing among processors and communication overheads. Design of a partitioner that obtains near optimal solutions satisfying such multiple criteria is difficult using any simple heuristic techniques other than simulated annealing.

关键词： Circuit simulation circuit partitioning simulated annealing hypercube architecture

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PARALLEL IMPLEMENTATION OF CIRCUIT SIMULATION

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International Journal of High Speed Computing 1990年第4期2卷 351-373页

作者： SRILATA RAMAN L.M. PATNAIK R. MALL Dept. of Electrical and Computer Engineering and Coordinated Science Laboratory University of Illinois at Urbana-Champaign IL 61801 U.S.A Microprocessor Applications Laboratory Indian Institute of Science Bangalore 560 012 India Supercomputer Education and Research Centre Indian Institute of Science Bangalore 560 012 India Dept. of Computer Science and Automation Indian Institute of Science Bangalore 560 012 India

The importance of circuit simulation in the design of VLSI circuits has channelised research work in the direction of finding methods to speedup this highly compute-intensive problem. On one hand, attempts have been made to find better algorithms and use faster hardware; and on the other hand, to use parallel architectures for accelerating the circuit simulation task. In this paper, we examine the various issues involved in parallelizing two well-known circuit simulation approaches – direct methods and relaxation methods. A number of parallel computer architectures which have been used for this purpose are also surveyed.

关键词： Circuit simulation VLSI circuit design direct method relaxation method parallel processing

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HIRECS: HYPERCUBE IMPLEMENTATION OF RELAXATION-BASED CIRCUIT SIMULATION

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International Journal of High Speed Computing 1989年第3期1卷 399-432页

作者： SRILATA RAMAN L.M. PATNAIK Dept. of Electrical and Computer Engineering and Coordinated Science Laboratory University of Illinois at Urbana-Champaign IL 61801 U.SA Dept. of Computer Science and Automation and Microprocessor Applications Laboratory Indian Institute of Science Bangalore 560 012 INDIA

Circuit simulation is a highly compute-intensive task as it involves solving thousands of ordinary differential equations (ODEs) describing the VLSI circuit under consideration. This paper describes an effort towards speeding up this task using a hypercube-based architecture. The paper focusses on the design and development of HIRECS (Hypercube Implementation of RElaxation-Based Circuit Simulation). HIRECS is based on the relaxation approach of solving the ODEs describing the circuit. The natural decomposition of the problem makes the relaxation algorithms amenable to parallel implementation. HIRECS employs the Waveform Relaxation (WR) algorithm. The special feature of WR algorithm is that the latency of the circuit can be exploited better, effecting a saving in the total computation time. The concept of ’windowing’ has been incorporated in HIRECS to effect a saving in the memory requirement. Another important feature of HIRECS is a novel synchronization scheme called partial synchronization. HIRECS runs on a DEC-1090 system and is developed using SIMULA. Performance studies of HIRECS based on parameters such as speedup, efficiency, and utilization of processors have been carried out. The performance evaluation of HIRECS in the simulation of some bench mark circuits like inverter chains and multiplexers indicates that a significant speedup, almost linear, can be obtained using a hypercube. For circuits with large number of nodes, such an implementation can result in tremendous saving in the computation time.

关键词： Circuit simulation Hypercube architecture Parallel processing Waveform relaxation

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MODELING METHODOLOGY FOR PERFORMANCE EVALUATION OF PARALLEL ARCHITECTURES A CASE STUDY, LCAP

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International Journal of High Speed Computing 1989年第4期1卷 563-601页

作者： J.P. PROST M. BECKER Post-Doc. Scientific Visitor IBM Corp. Data Systems Division Dept. 48B/MS 428 Neighborhood Rd Kingston NY 12401 USA Head of Computer Science Dept: Institut National des Télécommunications Les Epinettes 9 Rue Charles Fourier 91011 Evry Cedex France

This paper presents a modeling methodology devoted to the performance evaluation of parallel architectures. The methodology is based on the decomposition of the modeling process into seven stages. In each stage specific techniques, appropriate to parallel architectures, are applied, such as aggregation methods, a thorough distinction between the architecture model and the application program model, the constitution of program classes using data analysis techniques. The methodology is then illustrated through a case study, the loosely Coupled Array of Processors (lCAP) system, designed at IBM Kingston. Use of the lCAP model allows to predict the performance of the lCAP system, in terms of response time, resource utilization, waiting times, and to investigate many alternatives with regard to the system configuration (e. g. number of system components, component interconnection scheme, component characteristics), or to the parallel program structure (e. g. parallel task granularity, load imbalance).

关键词： loosely Coupled Array of Processors modeling methodology parallel architectures performance evaluation queueing network simulation

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Some aspects of a three dimensional shape descriptor function

Some aspects of a three dimensional shape descriptor functio...

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applications of Artificial Intelligence VI 1988

作者： Greenshields, Ian R. Hwang, Chi Jung Image Processing Laboratory Computer Applications and Research Center Dept. of Computer Science and Engineering University of Connecticut StorrsCT06268 United States

The paper describes a 3-dimensional Shape Descriptor Function (SDF) which is invariant under the action of SO(3). We concentrate here on the analytical derivation of the SSD, and show how certain requirements constrain both the nature of the SSD and the class of manifolds over which it can be defined. © 1988 Proceedings of SPIE - The International Society for Optical Engineering. All rights reserved.

关键词： computer architecture

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The NRL 100 GHz cold-cathode CARM

The NRL 100 GHz cold-cathode CARM

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13th International Conference on Infrared and Millimeter Waves 1987

作者： McCowan, R.B. Sullivan, C.A. Kirkpatrick, D.A. Gold, S.H. Manheimer, W.M. Fliflet, A.W. Black, W.M. Kinkead, A.K. Sucy, M. High Power Electromagnetic Radiation Branch Plasma Physics Division Naval Research Laboratory WashingtonDC20375-5000 United States Science Applications International Corporation McLeanVA22102 United States Dept. of Electrical and Computer Engineering George Mason University FairfaxVA22030 United States JAYCOR Inc. ViennaVA22180 United States

The design of a 10-20 MW, 40 nsec cyclotron auto-resonance maser experiment is presented. The basic components of the CARM are a novel 600 kV, 200 A. field emission gun and a "whispering gallery" mode ripple... 详细信息

关键词： Field emission cathodes

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