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International Conference on Properties and Applications of Properties and Applications of Dielectric Materials

作者： K. Imai A. Kanematsu M. Nawata M. Zahn Department of Electrical and Electronic Engineering Faculty of Science and Technology Meijo University Nagoya Japan Department of Electrical Engineering and Computer Science Laboratory for Electromagnetic and Electronic System High Voltage Research Laboratory Massachusetts Institute of Technology Cambridge MA USA

Kerr electro-optic field mapping measurements using the sensitive AC modulation method were made in liquid nitrogen. The steady-state electric fields between parallel stainless steel electrodes that had a gap of 7 mm are shown to be essentially uniform for voltages up to 70 kV with no significant space charge distortion. The Kerr constant B of liquid nitrogen is constant over the AC modulation frequency range of 1-20 kHz, while increasing above 20 kHz. This change of B with the modulation frequency coincides with the frequency-amplitude gain characteristic of the lock-in amplifier used, so that B is independent of the AC modulation frequency within the range of this study. B monotonically decreases with increasing temperature, T, thus decreasing liquid nitrogen density, rho , so that B is related linearly to rho /T. The polarizability anisotropy of liquid nitrogen is evaluated to be 8.3*10/sup -41/ F-m/sup 2/ from the slope of the B-( rho /T) characteristic, obtained from a simple physical model.< >

关键词： Frequency dependence Nitrogen Chirp modulation Frequency modulation Distortion measurement Electrooptic modulators Steady-state Electric fields Steel Electrodes

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Large Signal Analysis and Experimental Characteristics of Monolithic InP-Based W-Band HEMT Oscillators

Large Signal Analysis and Experimental Characteristics of Mo...

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European Conference on Microwave

作者： Youngwoo Kwon Dimitris Pavlidis Center for Space Terahertz Technology & Center for High Frequency Microelectronics Solid State Electronics Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

A large signal analysis method for simulating HEMT oscillators has been developed and applied to the design of a monolithic W-band HEMT oscillator. The analysis method uses measured small-signal S-parameters and employs a two-dimensional cubic spline interpolation routine and a harmonic balance technique to perform an accurate device modeling. The monolithic oscillators were fabricated using InAlAs/InGaAs heterostructures on InP substrate. A power level of 1.2 mW at 76.8 GHz was obtained using InAlAs/InGaAs heterostructures on InP substrate out of chips with 0.1 μm × 36 μm HEMT's. Comparisons between theoretical and experimental characteristics are also reported.

关键词： Signal analysis HEMTs Oscillators Indium compounds Indium gallium arsenide Indium phosphide Analytical models Signal design Harmonic analysis performance analysis

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TRANSPORT-EQUATION APPROACH FOR HETEROJUNCTION BIPOLAR-TRANSISTORS

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IEEE TRANSACTIONS ON ELECTRON DEVICES 1990年第3期37卷 519-529页

作者： TOMIZAWA, K PAVLIDIS, D Center of High-frequency Microelectronics Solid-State Electronic Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA Center of High Frequency Microelectronics Solid State Electronic Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

Transport equations for particle, momentum, and energy densities in two conduction bands are applied to a self-consistent numerical simulation of heterojunction bipolar transistors. Simple formulas for the relaxation frequencies, by which the variation of the conduction band energy and doping concentration in a heterojunction device are easily taken into account, are proposed. The electron transport in the AlGaAs/GaAs heterojunction bipolar transistor with two different collector structures is analyzed and discussed.< >

关键词： Equations Heterojunction bipolar transistors Frequency Electrons Laboratories Bipolar transistors Doping Gallium arsenide Transient analysis Monte Carlo methods

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ENSEMBLE MONTE-CARLO CHARACTERIZATION OF GRADED ALXGA1-XAS HETEROJUNCTION BARRIERS

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JOURNAL OF APPLIED PHYSICS 1990年第3期68卷 1114-1122页

作者： KAMOUA, R EAST, JR HADDAD, GI Center for High Frequency Microelectronics Solid State Electronics Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor Michigan 48109‐2122

Injection over and through heterojunction barriers is becoming increasingly more important in modern electronic devices. We consider the properties of graded AlxGa1?xAs heterojunction barriers using a self‐consistent ensemble Monte Carlo method. In this paper, we consider barriers with two doping levels, 1×1015 cm?3 and 1×1017 cm?3, and two barrier heights, 100 and 265 meV. The 100‐meV barrier resulted in small rectification at room temperature whereas the higher barrier exhibited considerable rectification. In both cases the structure with the lower doped barrier has resulted in a smaller current in both forward and reverse regions due to space‐charge effects. The energy and momentum distribution functions deviate from a Maxwellian distribution inside the barrier region and in general show two peaks: one is comprised mainly of electrons near equilibrium and the second arises mainly from ballistic electrons. The higher doped structure resulted in a faster electron relaxation toward equilibrium as a function of position because the electric field decreases rapidly in the barrier region.

关键词： ALUMINIUM ARSENIDES GALLIUM ARSENIDES HETEROJUNCTIONS DOPED MATERIALS MODULATION ELECTRONS IV CHARACTERISTIC THERMIONIC EMISSION SCHOTTKY BARRIER DIODES SCF CALCULATIONS MONTE CARLO METHOD ENSEMBLE

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ANALYTIC MODFET MODELS BEYOND THE TRIANGULAR WELL APPROXIMATION

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SOLID-STATE ELECTRONICS 1990年第7期33卷 885-891页

作者： DRUMMOND, TJ SHERWIN, ME Center for High Frequency Microelectronics Solid State Electronics Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI 48109-2122 U.S.A.

A new approach to modeling normal interface modulation doped field-effect transistors (MODFETs) is presented in which the 2-D electron gas density is integrated along the channel instead of the channel potential. With this approach we are able to implement a highly accurate polynomial description of the Fermi potential in the channel as a function of free electron density for arbitrary acceptor densities in GaAs channel. A substantial increase in the near threshold device current results. A carrier density dependent low field mobility is also incorporated into the model. These modifications are expected to result in an improved ability to estimate device characteristics from extrinsic material and device parameters.

关键词： Transistors, Field Effect

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Hierarchical multi-level fault simulation of large systems

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Journal of Electronic Testing 1990年第2期1卷 139-149页

作者： Saab, Daniel G. Mueller-Thuns, Robert B. Blaauw, David Rahmeh, Joseph T. Abraham, Jacob A. Center for Reliable and High Performance Computing Coordinated Science Laboratory University of Illinois at Urbana-Champaign Urbana 61801 IL United States Computer Engineering Research Center University of Texas at Austin Austin 78712 TX United States

This article discusses an approach for hierarchical multilevel fault simulation for large systems described at the transistor, gate, and higher levels. The approach reduces the memory requirement of the simulation drastically, thus allowing the simulation of circuits that are too large to simulate at one flat level on typical engineering workstations. This is achieved by exploiting the regularity and modularity found in a hierarchical circuit description that contains many repeated substructures. The hierarchical setup also allows flexible multilevel simulation: behavioral models can replace subcircuits at any level of the hierarchy for accelerated simulation. The simulation algorithms are at the switch level so that general MOS digital designs with bidirectional signal flow can be handled, and both stuck-at and transistor faults are treated accurately. The approach has been implemented in the hierarchical logic and fault simulation system, CHAMP, that runs under UNIX on SUN-3 and SUN-4 workstations. It has been used successfully for simulating and fault grading a large commercial microprocessor. © 1990 Kluwer Academic Publishers.

关键词： fault simulation multilevel simulation testing VLSI design

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A probabilistic model for the evaluation of fault-tolerant multiprocessor systems using concurrent error detection

A probabilistic model for the evaluation of fault-tolerant m...

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Advanced Signal Processing Algorithms, Architectures, and Implementations 1990

作者： Nair, V.S.S. Abraham, J.A. Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois at Urbana-Champaign UrbanaIL61801 United States Computer Engineering Research Center University of Texas at Austin AustinTX78758 United States

The analysis of fault-tolerant multiprocessor systems that use concurrent error detection (CED) schemes is much more difficult than the analysis of conventional fault-tolerant architectures. Various analytical techniques have been proposed to evaluate CED schemes deterministically. However, these approaches are based on the worst-case assumptions related to the failure of system components. Often, the evaluation results are not good measures for comparing the fault tolerance capabilities of a system. In this paper, we develop a probabilistic approach to evaluate and compare fault-tolerant multiprocessor systems. Various probabilities associated with CED schemes are identified and used in the framework of the matrix-based model which we had proposed previously. Based on these probabilistic matrices, we analytically derive estimates for the fault tolerance capabilities of various systems. © 1990 SPIE. All rights reserved.

关键词： Fault tolerance

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Fault grading of large digital systems

Fault grading of large digital systems

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： D.G. Saab R.B. Mueller-Thuns D. Blaauw J.T. Rahmeh J.A. Abraham Center for Reliable and High Performance Computing Coordinated Science Laboratory University of Illinois Urbana IL USA Computer Engineering Research Center Depatment of Electrical and Computer Engineering University of Texas Austin Austin TX USA

Cost-effective and accurate fault simulation of very large digital designs on engineering workstations is proposed. The hierarchical approach reduces memory requirements drastically by storing the structure of common repeated subcircuits only once. The approach allows flexible multilevel simulation. The simulation algorithms are at the switch-level so that general MOS digital designs with bidirectional signal flow can be handled, and both stuck-at and transistor faults are treated accurately. The fault simulation algorithms have been implemented as a prototype that was used to determine the fault grade of a model of the Motorola 68000 microprocessor on SUN Microsystems workstations.< >

关键词： Digital systems Circuit simulation Circuit faults Computational modeling Switches Circuit testing MOSFETs Logic circuits Adders Workstations

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Automatic classification of node types in switch-level descriptions

Automatic classification of node types in switch-level descr...

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： D.T. Blaauw P. Banerjee J.A. Abraham Center for Reliable an High Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA Department of Electrical & Computer Engineering University of Texas Austin Austin TX USA

In switch-level simulation, nodes carry a charge on their parasitic capacitance from one evaluation to the next, which gives them a memory quality. A node is classified as temporary if its memory aspect is lost and cannot affect the circuit operation, whereas a node is classified as a memory node if the memory of the node is maintained and can affect the circuit operation. Accurate classification of nodes into temporary and memory nodes increases the performance of compiled simulators and high-level model generators. An approach for reliable automatic classification of nodes in a switch-level description is introduced. Both an exhaustive, exponential-time algorithm and a polynomial-time heuristic are presented. The heuristic was implemented and tested for several large circuits, including a commercial microprocessor. For this processor, the proposed heuristics identified an average of 92% of all nodes as temporary nodes. The heuristic was applied in a high-level model generator and significantly increased its performance.< >

关键词： Circuit simulation Parasitic capacitance Circuit testing Maintenance Polynomials Switching circuits Switched capacitor circuits Joining processes Capacitance measurement Size measurement

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InP Based Monolithic Integrated HEMT Amplifiers and Their Material Sensitivity

InP Based Monolithic Integrated HEMT Amplifiers and Their Ma...

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European Conference on Microwave

作者： Matthias Weiss Geok Ing Ng Dimitris Pavlidis Center for Space Terahertz Technology & Center for High Frequency Microelectronics Solid State Electronics Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA Center for Space Terahertz Technology & Center for High Frequency Microelectronics Solid State Electronics Laboratory Department of Electrical Engineering and Computer Science The University of Michigan Ann Arbor Michigan 48109-2122

Experimental results on InP based In0.53+xGa0.47-xAs/In0.52Al0.48As HEMT monolithic integrated amplifiers are reported demonstrating the feasibility of this technology. Strained heteroepitaxy (x≥0.0) proved to enhance the device performance and upper frequency limits and was used for the MMIC-realization. More than 15 dB of gain were obtained from 6 to 9.5 GHz. The maximum gain was 22 dB and the return loss better than - 10 dB. In spite of the strained heteroepitaxy which can raise material control questions for MMIC realizations the experimental results for the samples (x=0.07 and x=0.22) showed good agreement with design objectives.

关键词： Indium phosphide HEMTs Frequency Indium gallium arsenide Indium compounds Gain Gallium arsenide Substrates Composite materials Degradation

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