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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Hangyan Guo Fan Yang Zherui Zhang Runhua Wang Junhua Liu Huailin Liao Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University

ISBN: (纸本)9781467397209

This paper presents a novel fractional-N digital PLL structure with a digitally controlled phase interpolator(DPI) and a time-to-digital converter(TDC). In this structure, a short bit-width DPI and a short bit-width TDC are combined to achieve high phase resolution and low in-band phase noise. Moreover, since the DPI readily achieves 360° phase range and the TDC provides good linearity, no extra complex calibration is needed, which simplifies the design and saves power and chip area. Designed in a 55-nm CMOS technology, the proposed digital PLL achieves-103 d Bc/Hz in-band phase noise at 2.4 GHz output frequency. It consumes 2.4 mW from a 1.2-V supply and occupies 0.18 mm2 active chip area.

关键词： A Low-Power and Small Chip-Area Fractional-N Digital PLL with Combination of DPI and TDC PLL

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A 7.9 fJ/conversion-step 10-bit 125 MS/s SAR ADC with Simplified Power-efficient Digital Control Logic 13

A 7.9 fJ/conversion-step 10-bit 125 MS/s SAR ADC with Simpli...

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Mingxiao He Fan Yang Xiucheng Hao Le Ye Huailin Liao Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University

ISBN: (纸本)9781467397209

This paper presents a 7.9 fJ /conversion-step 10-bit 125 MS/s successive approximation register(SAR) analog-to-digital converter(ADC) on the basis of a monotonic capacitor switching procedure. Simplified power-efficient digital control logic, multi-layer sandwich capacitor structure and high-speed level-shift bootstrapped sampling-and-holding(S/H) blocks are employed to achieve high performance with low power consumption. The prototype is implemented in 55 nm standard CMOS process, occupying an active area of 0.18 mm × 0.20 mm. Post simulation results show that an SNDR of 54.01 d B and an ENOB of 8.7 bit can be achieved by consuming 0.41 mW of the ADC core from a 1.2 V supply, and a figure of merit(FOM) of 7.9 fJ /conversion-step.

关键词： ADC SAR A 7.9 fJ/conversion-step 10-bit 125 MS/s SAR ADC with Simplified Power-efficient Digital Control Logic

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Electric field tuning spin splitting in topological insulator quantum dots doped with a single magnetic ion

arXiv

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arXiv 2018年

作者： Li, Xiaojing Wu, Zhenhua Lou, Wenkai College of Physics and Energy Fujian Normal University Fuzhou350007 China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China SKLSM Institute of Semiconductors Chinese Academy of Sciences Beijing100083 China

We investigate theoretically the electron spin states in disk-shaped HgTe topological insulator quantum dots (TIQDs) containing a single magnetic Mn2+ ion. We show that the energy spectrum and the electron density distribution of the topological edge states in HgTe TIQD can be modulated significantly by the position of the magnetic Mn2+ ion. The numerical results further demonstrate that the electric fields not only tune the spin splittings of edge states via the sp-d exchange interaction between the electron (hole) and the magnetic Mn2+ ion but also give rise to the bright-to-dark transitions and anti-crossing behaviors in the photoluminescence (PL) spectra. Such spin properties of HgTe TIQDs with single Mn2+ ion as illustrated in this work could offer a new platform for topological electro-optical devices. Copyright © 2018, The Authors. All rights reserved.

关键词： Nanocrystals

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P-10.4: Tuning Threshold Voltage of α-IGZO TFTs by Employing an Organic Molecular Doping

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SID Symposium Digest of Technical Papers 2019年第S1期50卷

作者： Yanjie Wang Jiawei Wang Liang Wang Chao Jiang CAS Key Laboratory of Standardization and Measurement for Nanotechnology CAS Center for Excellence in Nanoscience National Center for Nanoscience and Technology Beijing 100190 China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing 100029 China

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Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process

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Science China Earth Sciences 2016年第12期59卷 166-174页

作者： Guangyi LU Yuan WANG Lizhong ZHANG Jian CAO Xing ZHANG Key Laboratory of Microelectronie Devices and Circuits(MoE) Institute of MicroelectronicsPeking UniversityBeijing 100871China

This work presents the design of a novel static-triggered power-rail electrostatic discharge(ESD)clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is firstly discussed. Based on the discussion, a novel power-rail ESD clamp circuit utilizing the static ESD detection mechanism is proposed. By skillfully incorporating a thyristor delay stage into the trigger circuit(TC), the proposed circuit achieves the best ESD-conduction behavior while consuming the lowest leakage current(Ileak) at the normal bias voltage among all investigated circuits in this work. In addition, the proposed circuit achieves an excellent false-triggering immunity against fast power-up pulses. All investigated circuits are fabricated in a 65-nm CMOS process. Performance superiorities of the proposed circuit are fully verified by both simulation and test results. Moreover, the proposed circuit offers an efficient on-chip ESD protection scheme considering the worst discharge case in the utilized process.

关键词： electrostatic discharge （ESD） power-rail ESD clamp circuit detection mechanism transient-noise immunity false triggering transmission line pulsing （TLP） test

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Electric field modified Arrhenius description of charge transport in amorphous oxide semiconductor thin film transistors

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Physical Review B 2018年第24期98卷 245308-245308页

作者： Wei Wang Guangwei Xu M. Delwar H. Chowdhury Hong Wang Jae Kwang Um Zhuoyu Ji Nan Gao Zhiwei Zong Chong Bi Congyan Lu Nianduan Lu Writam Banerjee Jiafeng Feng Ling Li Andrey Kadashchuk Jin Jang Ming Liu Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing 100029 China Jiangsu National Synergetic Innovation Center for Advanced Materials (SICAM) Nanjing 210009 China Department of Information Display Advanced Display Research Center Kyung Hee University Korea Key Laboratory of Wide Band Gap Semiconductor Materials and Devices Xidian University China State Key Laboratory of Magnetism Institute of Physics of Chinese Academy of Sciences Beijing 100029 China Institute of Physics National Academy of Sciences of Ukraine Prospect Nauky 46 03028 Kyiv Ukraine IMEC Kapeldreef 75 3001 Leuven Belgium

While it is known that the charge-carrier mobility in amorphous metal oxide semiconductor thin film transistors (TFT) deviates from Arrhenius temperature dependence, we found that the Hall mobility measured in amorphous In-Ga-Zn-O (a-IGZO) follows an Arrhenius relation surprisingly well. We explain these observations by the effect of strong vertical electric field created by the gate voltage, which facilitates direct tunneling of trapped carriers into the conductive band and leads to virtually temperature independent mobility. We present a generalized Arrhenius model based on the effective temperature concept. We show that our model allows quantitative description of the temperature dependence of the mobility in a-IGZO TFTs over a broad temperature range.

关键词： Carrier dynamics Field-effect transistors Transport phenomena Amorphous semiconductors Oxides

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Simulation of doping effect for HfOi-based RRAM based on first-principles calculations

Simulation of doping effect for HfOi-based RRAM based on fir...

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2017 International Conference on Simulation of Semiconductor Processes and devices, SISPAD 2017

作者： Wei, Wei Chuai, Xichen Lu, Nianduan Wang, Yan Li, Ling Ye, Cong Liu, Ming Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing100029 China Hubei University Wuhan430062 China University of Chinese Academy of Sciences Beijing100049 China

ISBN: (纸本)9784863486102

A physical model of revealing the charge carrier transport characteristics based on first-principles calculations has been proposed for oxide-based RRAM. Based on the proposed model, we have investigated the influence of different kinds of dopants on transport characteristics in HfO2-based RRAM. The present method will be contributed to clearly understand the dopant effect, and then tune the RRAM performance and better design RRAM device. © 2017 The Japan Society of Applied Physics.

关键词： Activation energy

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Corrections to “A Novel Tunnel FET Design Through Adaptive Bandgap Engineering With Constant Sub-Threshold Slope Over 5 Decades of Current and High ${I_{{\mathrm {ON}}}}/{I_{{\mathrm {OFF}}}}$ Ratio” [May 17 540-543]

IEEE Electron Device Letters

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IEEE Electron Device Letters 2018年第4期39卷 638-638页

作者： Yang Zhao Chunlei Wu Qianqian Huang Cheng Chen Jiadi Zhu Lingyi Guo Rundong Jia Zhu Lv Yuchao Yang Ming Li Ru Huang Key Laboratory of Microelectronics Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China

In the above paper, there is an error in the information of corresponding author’s email address. The corrected corresponding author’s email address information is provided.

关键词： Germanium silicon alloys Field effect transistors TFETs Low-power electronics Semiconductor device manufacture

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Multi-VT design of vertical channel nanowire FET for sub-10nm technology node 7

Multi-VT design of vertical channel nanowire FET for sub-10n...

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7th IEEE International Nanoelectronics Conference, INEC 2016

作者： Chen, Gong Li, Ming Fan, Jiewen Yang, Yuancheng Zhang, Hao Huang, Ru Key Laboratory of Microelectronic Devices Circuits Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)9781467389693

In this work, a feasible multi-VT modulation strategy in vertical nanowire FETs (VNWFETs) combining asymmetric halo doping with nanowire diameter is proposed and verified by TCAD simulation. The results show that halo configuration close to source side exhibits larger VT-tuning range and better SCE controlling. Moreover, adjustment of halo doping concentration and nanowire diameters can be adopted to provide at least three VT choices for 7nm technology node. It is demonstrated that VNWFETs is quite promising for SOC application. © 2016 IEEE.

关键词： Nanowires

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Leakage Current Analysis Using High Resistivity Silicon Gated Diodes For PIN Detectors Application 13

Leakage Current Analysis Using High Resistivity Silicon Gate...

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Hao Wang Min Yu Baohua Shi Yahuan Huang Xinyang Zhao Yufeng Jin National Key Laboratory of Nano/Micro Fabrication Technology Key Laboratory of Microelectronic Devices and Circuits(MOE) Institute of Microelectronics Peking University

ISBN: (纸本)9781467397209

Ultra-thick and ultra-thin Silicon PIN detectors are specially applied in high particles detections. The corresponding leakage current is investigated. The ultra-thick and ultra-thin gated diodes structures based on high resistivity silicon substrates are fabricated and tested to analyses the reverse leakage current for silicon PIN detectors application. It is concluded that the contribution of the generation current in the main junction depletion region is more significant in the ultra-thick structures, while the contribution of the generation current generated at the silicon-oxide interface is more evident in the ultra-thin structures.

关键词： Leakage Current Analysis Using High Resistivity Silicon Gated Diodes For PIN Detectors Application PIN

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