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Ge surface passivation by GeO2 fabricated by N2O plasma oxidation

Science China(Information Sciences) 2015年第4期58卷 143-147页

作者： LIN Meng AN Xia LI Ming YUN QuanXin LI Min LI Zhi Qiang LIU PengQiang ZHANG Xing HUANG Ru Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

In this paper, Ge surface passivation by Ge O2 grown by N2 O plasma oxidation is presented and experimentally demonstrated. Results show that stoichiometrically Ge O2 can be achieved by N2 O plasma oxidation at 350°C. The transmission electron microscope observation reveals that the Ge O2/Ge interface is automatically smooth and the thickness of Ge O2is～0.9 nm with 120 s N2 O plasma oxidation. The interface state density of Ge surface after N2 O plasma passivation is about～3×1011 cm-2e V-1. With Ge O2 passivation,the hysteresis of MOS capacitor with Al2O3 as gate dielectric is reduced to～55 m V, compared to 130 m V of the untreated one. The Fermi-level at Ge O2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage, which is promising for high performance NMOSFETs fabrication.

关键词： Ge passivation Ge O 2 N 2 O plasma oxidation

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Synthesis of Highly Uniform Monolayer Graphene by Etching the Multilayer Spots for Electronic devices 13

Synthesis of Highly Uniform Monolayer Graphene by Etching th...

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Pei Peng Zidong Wang Zhongzheng Tian Yuehui Jia Xin Gong Jianhong Song Liming Ren Yunyi Fu Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Materials Physics Laboratory State Key Laboratory for Mesoscopic Physics School of Physics Peking University School of Electronic and Computer Engineering Peking University Shenzhen Graduate School

ISBN: (纸本)9781467397209

We demonstrate a facile method to grow highly uniform monolayer graphene films on copper foils by atmospheric pressure chemical vapor deposition（APCVD）. The technique in this method includes lowering flow ratio of methane/hydrogen and extending exposure time to hydrogen. All the multilayer islands will be etched away by hydrogen during this growth process, resulting in obtaining highly uniform monolayer graphene. A mechanism for the suppression of mutilayer spots based on the etching effect of hydrogen is *** electron and hole room-temperature mobilities for the back-gated graphene transistors are up to about 3800cmVs and 3300 cmVs, respectively.

关键词： Synthesis of Highly Uniform Monolayer Graphene by Etching the Multilayer Spots for Electronic devices Graphene

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Barrier tunneling of the loop-nodal semimetal in the hyperhoneycomb lattice

arXiv

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arXiv 2018年

作者： Guan, Ji-Huan Zhang, Yan-Yang Lu, Wei-Er Xia, Yang Li, Shu-Shen SKLSM Institute of Semiconductors Chinese Academy of Sciences P.O. Box 912 Beijing100083 China School of Physical Sciences University of Chinese Academy of Sciences Beijing101408 China Synergetic Innovation Center of Quantum Information and Quantum Physics University of Science and Technology of China Hefei Anhui230026 China School of Microelectronics University of Chinese Academy of Sciences Beijing101408 China Microelectronic Instrument and Equipment Research Center Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China College of Materials Science and Opto-Electronic Technology University of Chinese Academy of Sciences Beijing101408 China

We theoretically investigate the barrier tunneling in the three-dimensional model of the hyperhoneycomb lattice, which is a nodal-line semimetal with a Dirac loop at zero energy. In the presence of a rectangular potential, the scattering amplitudes for different injecting states around the nodal loop are calculated, by using analytical treatments of the effective model, as well as numerical simulations of the tight binding model. In the low energy regime, states with remarkable transmissions are only concentrated in a small range around the loop plane. When the momentum of the injecting electron is coplanar with the nodal loop, nearly perfect transmissions can occur for a large range of injecting azimuthal angles if the potential is not high. For higher potential energies, the transmission shows a resonant oscillation with the potential, but still with peaks being perfect transmissions that do not decay with the potential width. These robust transports of the loop-nodal semimetal can be approximately explained by a momentum dependent Dirac Hamiltonian. Copyright © 2018, The Authors. All rights reserved.

关键词： Potential energy

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Enhancement of Photocurrent in Suspended Monolayer Graphene 13

Enhancement of Photocurrent in Suspended Monolayer Graphene

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Jianhong Song Xin Gong Pei Peng Zidong Wang Zhongzheng Tian Yuehui Jia Liming Ren Yunyi Fu Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Materials Physics Laboratory State Key Laboratory for Mesoscopic Physics School of Physics Peking University School of Electronic and Computer Engineering Peking University Shenzhen Graduate School

ISBN: (纸本)9781467397209

The photocurrent in graphene has drawn much attention in recent years. The mechanisms of its production vary in different situations, such as at the interfaces of monolayer-bilayer junction or p-n junction. Here we demonstrate photocurrent generation in graphene-based field-effect transistors(GFETs) with a partially suspended area. Both Raman and photocurrent mapping were performed after a laser-induced doping under vacuum at room temperature. The resulting photocurrent in the suspended area is an order of magnitude larger than that in the supported area. The difference in photocurrent may be attributed to the thermoelectric effect.

关键词： Raman Enhancement of Photocurrent in Suspended Monolayer Graphene

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GIDL Challenge of GAA SNWT For Low Power Application

GIDL Challenge of GAA SNWT For Low Power Application

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Ming Li Jiewen Fan Yuancheng Yang Gong Chen Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

In this paper, the challenge of gate-all-around nanowire transistor for low power application is uncovered and discussed from experimental and TCAD simulation. For promising low power application, gate-all-around nanowire transistor faces more difficulties than expected due to abnormal gate-induced-drain-leakage current behavior. The study shows that as nanowire diameter shrinks, GIDL current will become worse rather than suppressed. The gate coupling modulated drain-to-body electric field is found responsible for the increased GIDL current in the extremely scaled nanowire. To overcome the challenge of GAA SNWT in low power application, a practical design is proposed by optimization of overlap length and drain junction gradient considering the trade-off between short channel effect and performance.

关键词： GIDL Challenge of GAA SNWT For Low Power Application

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A review for compact model of graphene field-effect transistors

arXiv

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arXiv 2017年

作者： Lu, Nianduan Wang, Lingfei Li, Ling Liu, Ming Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China Nanjing210009 China

Graphene has attracted enormous interests due to its unique physical, mechanical, and electrical properties. Specially, graphene-based field-effect transistors (FETs) have evolved rapidly and are now considered as an option for conventional silicon devices. As a critical step in the design cycle of modern IC products, compact model refers to the development of models for integrated semiconductor devices for use in circuit simulations. The purpose of this review is to provide a theoretical description of current compact model of graphene field-effect transistors. Special attention is devoted to the charge sheet model, drift-diffusion model, Boltzmann equation, density of states (DOS), and surface-potential-based compact model. Finally, an outlook of this field is briefly *** Codes 65Zxx Copyright © 2017, The Authors. All rights reserved.

关键词： Field effect transistors

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SAPTL –based Robust Sub-threshold Adder Circuit Design 13

SAPTL –based Robust Sub-threshold Adder Circuit Design

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Qi Zhang Yuping Wu Lan Chen Xuelian Zhang Weicheng Shi Institute of Microelectronics of Chinese Academy of Sciences Beijing Key Laboratory of 3D & Nano IC Design Automation Technology Key Laboratory of Microelectronic Devices & Integrated Technology CAS

ISBN: (纸本)9781467397209

Process variation results in up to an order of magnitude variation in on/off ratios, which significantly depresses the yield of the sub-threshold circuits. This paper presents low power sub-threshold adders using sense amplifier-based pass transistor logic(SAPTL). Based on the simulations in 130 nm CMOS process, the proposed two-phase synchronous SAPTL adder exhibits stronger robustness to process variations when compared to the ripple carry adder using standard cell circuits. And the adder based on ADSA-SAPTL features much less power consumption than synchronous SAPTL adder.

关键词： based Robust Sub-threshold Adder Circuit Design SAPTL

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Layout Decomposition Algorithms for Double Patterning Lithography 13

Layout Decomposition Algorithms for Double Patterning Lithog...

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Xuelian Zhang Yuping Wu Lan Chen Qi Zhang Weicheng Shi Institute of Microelectronics of Chinese Academy of Sciences Beijing Key Laboratory of 3D & Nano IC Design Automation Technology Key Laboratory of Microelectronic Devices & Integrated Technology CAS

ISBN: (纸本)9781467397209

We present an efficient layout decomposition flow and the corresponding optimization algorithms to minimize the stitches for double patterning *** the given power/ground preprocessing method for the flow reduces the complexity, and improves the speed and quality to the layout decomposition. Experiments show that our algorithms can effectively get the better results compared with other reported algorithms.

关键词： Estimation Field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Effects of heavy ion irradiation on ultra-deep-submicron partially-depleted SOI devices

引用

Journal of Semiconductors 2015年第11期36卷 39-43页

作者：武唯康安霞谭斐冯慧陈叶华刘静静张兴黄如 Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

The effects of the physical damages induced by heavy ion irradiation on the performance of partiallydepleted SOI devices are experimentally investigated. After heavy ion exposure, different degradation phenomena are observed due to the random strike of heavy ions. A decrease of the saturation current and transconductance,and an enhanced gate-induced drain leakage current are observed, which are mainly attributed to the displacement damages that may be located in the channel, the depletion region of the drain/body junction or the gate-to-drain overlap region. Further, PDSOI devices with and without body contact are compared, which reveals the differences in the threshold voltage shift, the drain-induced barrier lowing effect, the transconductance and the kink effect. The results may provide a guideline for radiation hardened design.

关键词： heavy ion displacement damages PDSOI performance degradation

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Line-edge roughness induced single event transient variation in SOI Fin FETs

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Journal of Semiconductors 2015年第11期36卷 25-29页

作者：武唯康安霞蒋晓波陈叶华刘静静张兴黄如 Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

The impact of process induced variation on the response of SOI Fin FET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When Fin FET biased at OFF state configuration（Vgs D0, Vds DVdd/ is struck by a heavy ion, the drain collects ionizing charges under the electric field and a current pulse（single event transient, SET） is consequently formed. The results reveal that with the presence of line-edge roughness（LER）, which is one of the major variation sources in nano-scale Fin FETs, the device-to-device variation in terms of SET is observed. In this study, three types of LER are considered： type A has symmetric fin edges, type B has irrelevant fin edges and type C has parallel fin edges. The results show that type A devices have the largest SET variation while type C devices have the smallest variation. Further, the impact of the two main LER parameters,correlation length and root mean square amplitude, on SET variation is discussed as well. The results indicate that variation may be a concern in radiation effects with the down scaling of feature size.

关键词： heavy ion irradiation single event transient variation line-edge roughness SOI Fin FET

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