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Asia Pacific Conference on Postgraduate Research in microelectronics & Electronics (PrimeAsia)

作者： Xiongbo Zhao Song Jia Yuan Wang Guirong Wu Fengfeng Wu Kai Yang Key Laboratory of Microelectronics Devices and Circuits Institute of Microelectronics Peking University Beijing China

RapidIO is an open standard that provides high-performance interconnect for chip-to-chip, board-to-board, and chassis-to-chassis communications. In this paper, we present an executable RapidIO interconnect in which an improved Buffer structure based on flow control is put forward. It helps to provide a smooth data flow, strong built-in error detection and error recovery mechanisms. It is tested to increase utilization and lower packet latency. And it can be applied to reliable and high speed embedded system communications.

关键词： Physical layer Embedded system Protocols Receivers Transmitters Integrated circuit interconnections Performance evaluation

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Analysis of LDMOS-SCR ESD protection device for 60V SOI BCD technology

Analysis of LDMOS-SCR ESD protection device for 60V SOI BCD ...

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IEEE Conference on Electron devices and Solid-State circuits

作者： Peng Zhang Yuan Wang Song Jia Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroeIectronics Peking University Beijing China

A study of two major types of LDMOS-SCR electrostatic discharge protection devices for 60V SOI BCD technology is presented. The difference of the P-anode implant positions influences the triggering mechanism of the two types of devices. The relationship between I-V behavior under ESD and the device parameter is studied. Heat dissipation capability of the device is also presented.

关键词： Anodes Robustness

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Design of RapidIO logical core based on safety arbitration mechanisms

Design of RapidIO logical core based on safety arbitration m...

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Asia Pacific Conference on Postgraduate Research in microelectronics & Electronics (PrimeAsia)

作者： Wu Fengfeng Jia Song Yang Kai Zhao Xiongbo Wu Guirong Key Laboratory of Microelectronics Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China

RapidIO is an emerging high-performance and point-to-point packetized interconnection technology. In this paper, the design of the logical core based on safety arbitration mechanisms is described in detail. The packing and unpacking of I/O Logical, Message Passing and Globally Shared Memory transactions are achieved. Excellent average data transfer rates, up to 7.8 bytes per cycle are reached in certain transactions with 256-byte data payloads, meanwhile the data efficiencies are more than 95%. Moreover, maintenance read transactions targeted at local capability and status registers can be executed in a lower latency compared with the reference design.

关键词： Maintenance engineering Delay Payloads Receivers Transmitters Registers Safety

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A novel nitrogen-doped SiOx resistive switching memory with low switching voltages

A novel nitrogen-doped SiOx resistive switching memory with ...

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IEEE Silicon Nanoelectronics Workshop (SNW)

作者： Dejin Gao Lijie Zhang Ru Huang Runsheng Wang Dongmei Wu Yongbian Kuang Yu Tang Zhe Yu Albert Z. H. Wang Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China Department of Electrical Engineering University of California Riverside CA USA

In summary, a novel RRAM with the structure of Cu/Si x O y N z /W was first fabricated and its characteristics are thoroughly investigated. The new device exhibited low switching voltages and low reset currents, demonstrating its potential for low-power applications. Repeatable unipolar resistive switching characteristics in terms of high off/on resistance ratio and good retention capability were observed. The switching mechanism of the device was analyzed and can be explained by the formation and rupture of vacancy filaments.

关键词： Copper Resistance Switches Nitrogen Temperature Electrodes Voltage measurement

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Influence of boundary force on the performance of gate-all-around Ge (110) NW FETs with HfO2 gate insulator

Influence of boundary force on the performance of gate-all-a...

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IEEE International Nanoelectronics Conference (INEC)

作者： Honghua Xu Xiaoyan Liu Gang Du Yuhui He Chun Fan Ruqi Han Jinfeng Kang Institute of Microelectronics Key Laboratory of Microelectronic Devices and Circuits Ministry of Education Peking University Beijing China Institute of Microelectronics Peking University Beijing China Key Laboratory of Nanofabrication and Novel Devices Integration Technology Institute of Microelectronics Chinese Academy and Sciences Beijing China Computer Center Peking University Beijing China

ISBN: (纸本)9781424435432;9781424435449

We calculate valence band structures and transport property of HfO 2 gate dielectric surrounded Ge (110) nanowire with a radial force at the boundary of the insulator. The radial force pushes the valence subbands downwards. Most of hole effective masses of top five subbands decrease and densities of states' peaks move down as the force increases. The hole mobility in Ge (110) NW significantly increases with higher force values.

关键词： FETs Hafnium oxide Dielectrics and electrical insulation Capacitive sensors Effective mass Nanoscale devices Electrodes Lattices Voltage High-K gate dielectrics

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Novel mixed-voltage I/O buffer with thin-oxide CMOS transistors

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Journal of Semiconductors 2009年第7期30卷 83-85页

作者：俞波王源贾嵩张钢刚 Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

This paper presents a novel mixed-voltage I/O buffer without an extra dual-oxide CMOS *** mixed-voltage I/O buffer with a simplified circuit scheme can overcome the problems of leakage current and gateoxide reliability that the conventional CMOS I/O buffer *** design is realized in a 0.13-μm CMOS process and the simulation results show a good performance increased by ～34% with respect to the product of power consumption and speed.

关键词： mixed-voltage I/O buffer multi-power domain thin-oxide CMOS

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Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit

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Journal of Semiconductors 2009年第12期30卷 128-132页

作者：刘振贾嵩王源吉利久张兴 Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter （ADC） A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm^2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.

关键词： analog-to-digital converter low power fully-folding mixed-averaging distributed T/H circuit bit synchronization

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A VCO sub-band selection circuit for fast PLL calibration

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Journal of Semiconductors 2009年第8期30卷 153-155页

作者：宋颖王源贾嵩赵宝瑛 Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of MicroelectronicsPeking University

A novel voltage controlled oscillator （VCO） sub-band selection circuit to achieve fast phase locked loop （PLL） calibration is presented, which reduces the calibration time by measuring the period difference directly and accomplishing an efficient search for an optimum VCO sub-band. The sub-band selection circuit was implemented in a 0.18 μm CMOS logic process with a PLL using an 8 sub-band VCO. The measured calibration time is less than 3 μs in a VCO frequency range from 600 MHz to 2 GHz. The proposed circuit consumes 0.64 mA at most.

关键词： PLL VCO calibration

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Numerical simulation on novel nano-scale lateral double-gate tunneling field effect transistor

Numerical simulation on novel nano-scale lateral double-gate...

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IEEE International Nanoelectronics Conference (INEC)

作者： Frank He Haijun Lou Wang Zhou Lin Chen Yiwen Xu Hao Zhuang Xinnan Lin TSRC Key Laboratory of Microelectronic Devices and Circuits Institute of Micro-electronics School of Electronics and Computer Science Peking University China Key Laboratory of Integrated Microsystems Peking University Shenzhen China

ISBN: (纸本)9781424435432

A novel nano-scale lateral double-gate tunneling field effect transistor (LDG-TFET) is proposed in this paper and its performance is shown through two dimensional device numerical simulations. The study result demonstrates that this new tunneling transistor allows for the steeper sub-threshold swings, e.g. below 60 mV/Dec, the super low supply voltage, e.g. operable at VDD <0.2V and the high ratio between the turn-on and turn-off current for the availability of high-k/metal stack materials. This tunneling field effect transistor may be integrated with present CMOS process and architecture with some specific applications such as memories because of the low turn-off current and when the delay is truly determined by interconnects because of its high turn-on/turn off ratio, which are important for next generation of micro-power and ultra-low integrated circuits.

关键词： Numerical simulation Tunneling Double-gate FETs Nanoscale devices Low voltage Availability High K dielectric materials High-K gate dielectrics Inorganic materials CMOS process

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A low-noise interface circuit for MEMS vibratory gyroscope

A low-noise interface circuit for MEMS vibratory gyroscope

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Ran Fang Guannan Wang Dunshan Yu Yuan Ju Wengao Lu Lijiu Ji Zhongjian Chen Chang Liu Key Laboratory of Microelectronic Devices and Circuit Department of Microelectronics Peking Univer School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA 30332

ISBN: (纸本)9781424457977

A CMOS ASIC has been designed and implemented for readout and control of MEMS vibratory gyroscopes. A low noise design is achieved by using the technique of sinusoidal chopper stabilization with a chopping frequency of 2MHz, which will effectively suppress the low frequency noise. A closed loop control method in driving mode is presented. The Chip is fabricated in a 0.35μm standard CMOS process with an area of 2.5×2.5mm2. The test is performed with a vibratory gyroscope on the condition of closed-loop control, and the measurement result shows a detecting resolution of 6aF in 100Hz bandwidth from a single 5V supply.

关键词： Gyroscopes Micromechanical devices Noise Capacitance Oscillators Application specific integrated circuits Low pass filters

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