A Ku-band power amplifier is successfully developed with an internal-matched single chip 6mm AlGaN/GaN high electron mobility transistors (HEMTs). LCL network together with microstrip circuits are used to directly mat...
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A Ku-band power amplifier is successfully developed with an internal-matched single chip 6mm AlGaN/GaN high electron mobility transistors (HEMTs). LCL network together with microstrip circuits are used to directly match the impedance of the 6mm GaN HEMTs to 50Ohm without using power combiner. Under the pulsed condition (100μs, 10%), the developed GaN HEMTs power amplifier delivers a 22W saturated output power with 7.6dB linear gain and 26.8% maximum power-added efficiency (PAE) with a drain voltage of 32V and at the frequency of 13.7GHz. To our best knowledge, the achieved high performance power amplifier is the state-of-the-art result ever reported for internal-matched 6mm gate width single chip GaN-based hybrid microwave integrated power amplifier at Ku-band.
Fermi level pinning(FLP) and dipole formation in TiN/HfO/SiO/Si stacks are investigated. The magnitude of FLP at Ti N/HfO interface is estimated to be V based on dipole theory using concepts of interfacial gap state...
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Fermi level pinning(FLP) and dipole formation in TiN/HfO/SiO/Si stacks are investigated. The magnitude of FLP at Ti N/HfO interface is estimated to be V based on dipole theory using concepts of interfacial gap states and charge neutrality level(CNL). The dipole amount at HfO/SiO interface is experimentally extracted to be +0.33 V. These results show that dipole formation at HfO/SiO interface is important for tuning flatband voltage of the TiN/HfO/SiO/Si stacks. Possible origin of dipole formation is demonstrated and attributed to be lower CNL of HfO compared with that of SiO/Si stacks.
Fermi level pinning(FLP)and dipole formation in TiN/HfO2/SiO2/Si stacks are *** magnitude of Fermi level pinning at TiN/HfO2 interface is estimated to be V based on dipole theory using concepts of interfacial gap stat...
Fermi level pinning(FLP)and dipole formation in TiN/HfO2/SiO2/Si stacks are *** magnitude of Fermi level pinning at TiN/HfO2 interface is estimated to be V based on dipole theory using concepts of interfacial gap states and charge neutrality *** dipole amount at HfO2/SiO2 interface is experimentally extracted to be +0.33 *** results show that dipole formation at HfO2/SiO2 interface is important for tuning flatband voltage of the TiN/HfO2/SiO2/Si stacks.
Diamond-like carbon (DLC) films as a new strain-capping material with compressive stress up to 12GPa for strained silicon technology were fabricated by filtered cathodic vacuum arc (FCVA) deposition system. The films...
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Diamond-like carbon (DLC) films as a new strain-capping material with compressive stress up to 12GPa for strained silicon technology were fabricated by filtered cathodic vacuum arc (FCVA) deposition system. The films’ compositions and bonding structures were characterized using multi-wavelength Raman spectroscopy. The relationship between intrinsic stress and G peak dispersion of the films’ Raman spectra were discussed. The results showed that the bias voltage applied to substrate during deposition determines films’ sp3 bonding content and intrinsic stress. Process compatibility of the DLC films with standard CMOS technology was confirmed by using WDXRF measurement. Also diffusion behavior of carbon atoms in DLC films with copper and silicon was studied with a Cu(200nm)/DLC(40nm)/silicon multilayer structure annealed at 500℃ in N2 atmosphere for an hour. At last, stress induced on silicon surface by DLC strips was characterized using surface sensitive UV-Raman spectroscopy. The results showed that DLC films with extremely high compressive stress have potential application in future CMOS strain engineering.
The black multi-crystalline silicon (mc-Si) has been successfully produced by plasma immersion ion implantation. The microstructure and the reflectance of the black mc-Si have been investigated by atomic force microsc...
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The black multi-crystalline silicon (mc-Si) has been successfully produced by plasma immersion ion implantation. The microstructure and the reflectance of the black mc-Si have been investigated by atomic force microscope and spectrophotometer, respectively. Results show that the black mc-Si exhibits a hillock structure with a low reflectance. Besides, with decreasing the diffusion temperature, the external quantum efficiency of the black mc-Si solar cell increases below ∼550 nm wavelength due to reduced surface recombination. The optimal conversion effieciency of the black mc-Si solar cell is 15.50% at the diffusion temperature of 825 °C. Furthermore, it is interesting to find that there are something different between black mc-Si and acid etched mc-Si on the impact of diffusion.
GaN-based high electron mobility transistors (HEMTs) have successfully demonstrated unprecedented potential in microwave power electronics applications, featuring both high saturation current and high breakdown voltag...
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GaN-based high electron mobility transistors (HEMTs) have successfully demonstrated unprecedented potential in microwave power electronics applications, featuring both high saturation current and high breakdown voltage. Especially, increasing the gate-drain distance is very beneficial to reduce the off-state leakage current for power switching devices. GaN HEMT devices with the gate-drain distance of 29μm have obtained very low off-state leakage current of 3.8μA at V DS =100V and reverse Schottky-gate leakage current of 2.93μA at V GD = -100V. After SiN x passivation, both leakage currents increase nearly one order of magnitude, which are 19.5μA and 14.34μA respectively. On the one hand, the SiN x dielectric layer decreases surface current leakage and suppresses the virtual-gate effect on the electric-field distribution. On the other hand, it increases the electric-field strength near the gate edge at the drain side, resulting in higher Schottky-gate leakage current. Anyway, GaN HEMT devices show a great potential to achieve breakdown voltage of several hundred volts. Further in combination with field-plate technique, the great reduction of peak electric field at gate edge is advantageous for highvoltage applications.
Silicon nanowire arrays(SiNWAs) are fabricated on polished pyramids of textured Si using an aqueous chemical etching *** silicon nanowires themselves or hybrid structures of nanowires and pyramids both show strong a...
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Silicon nanowire arrays(SiNWAs) are fabricated on polished pyramids of textured Si using an aqueous chemical etching *** silicon nanowires themselves or hybrid structures of nanowires and pyramids both show strong anti-reflectance abilities in the wavelength region of 300-1000 nm,and reflectances of 2.52%and less than 8%are achieved,respectively.A 12.45%SiNWAs-textured solar cell(SC) with a short circuit current of 34.82 mA/cm^2 and open circuit voltage(K_(oc)) of 594 mV was fabricated on 125×125 mm^2 Si using a conventional process including metal grid *** is revealed that passivation is essential for hybrid structure textured SCs,and K_(oc) can be enlarged by 28.6%from 420 V to 560 mV after the passivation layer is *** loss mechanism of SiNWA SC was investigated in detail by systematic comparison of the basic parameters and external quantum efficiency(EQE) of samples with different fabrication *** is proved that surface passivation and fabrication of a metal grid are critical for high efficiency SiNWA SC,and the performance of SiNWA SC could be improved when fabricated on a substrate with an initial PN junction.
In this paper,a GaN-based metal-semiconductor-metal planar inter-dig itated varactor is *** quality factor of the inter-digitated varactor with finger width of 0.25μm and space between fingers of 7μm on sapphire is ...
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ISBN:
(纸本)9781467324748
In this paper,a GaN-based metal-semiconductor-metal planar inter-dig itated varactor is *** quality factor of the inter-digitated varactor with finger width of 0.25μm and space between fingers of 7μm on sapphire is 31.9 at 100M Hz,and the tunable capacitance ranges fro m 0.19pF to *** characteristics of this varactor with different finger's widths and spaces are *** is shown that the maximu m capacitance depends on the total area of fingers and the min imu m capacitance lies on fingers'width and the space between *** either width or space is fixed,the minimu m capacitance decreases with the increase of the other one.
A novel Dynamic Element Matching(DEM)method is presented to improve the static and dynamic performance of Nyquist-rate current-steering digital to analog converter(DAC).Compared to conventional DEM methods,this ap...
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ISBN:
(纸本)9781467324748
A novel Dynamic Element Matching(DEM)method is presented to improve the static and dynamic performance of Nyquist-rate current-steering digital to analog converter(DAC).Compared to conventional DEM methods,this approach only increases or decreases the number of selected unit current sources randomly when the input code ***,signal dependent distortions can be eliminated efficiently at high sampling frequencies.A 6-bit current-steering DAC model adopting the proposed DEM coding method was built up to verify the performance in *** could reach a better SFDR(56dB)value and a better DNL(0.26LSB) and INL(0.45LSB)value compared with traditional DEM methods.
A phase interpolator(PI)-based clock data recovery(CDR)circuit for RapidIO application is presented,which avoids the coupled interference of *** the integration of a digital control cell,the complex and area consu...
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ISBN:
(纸本)9781467324748
A phase interpolator(PI)-based clock data recovery(CDR)circuit for RapidIO application is presented,which avoids the coupled interference of *** the integration of a digital control cell,the complex and area consumption has been reduced *** adaptive bandwidth PLL structure is adopted so that it can provide clocks of three frequencies while maintain a good jitter *** a 0.13um CMOS process,the circuit has a jitter of 11.2ps@3.125Gbps with a power consumption of 21.7mW under 1.2V,and the core circuit area is 0.16mm2.
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