In this paper, the random telegraph noise (RTN) statistics in silicon nanowire transistors (SNWTs) are comprehensively studied. The capture/emission time constants and probabilities are found to be strongly impacted b...
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In this paper, the random telegraph noise (RTN) statistics in silicon nanowire transistors (SNWTs) are comprehensively studied. The capture/emission time constants and probabilities are found to be strongly impacted by the quantum confinement in SNWTs, which cannot be fully explained by classical RTN theory. A full quantum RTN model for SNWTs is proposed for fundamental understanding of the experiments. The characteristics of non-stationary RTN in SNWTs under high-field biases are studied for the first time, based on the developed statistical trap-response (STR) characterization method. The trap capture probability is found to be much different from that of the quasi-stationary RTN, leading to large errors in circuit aging prediction if using traditional RTN distributions. These new understandings are critical for robust SNWT circuit design against RTN.
In this paper, a novel silicon-based T-gate Schottky barrier tunneling FET (TSB-TFET) is proposed and experimentally demonstrated. With enhanced electric field at source side through gate configuration for steeper sub...
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ISBN:
(纸本)9781457705069
In this paper, a novel silicon-based T-gate Schottky barrier tunneling FET (TSB-TFET) is proposed and experimentally demonstrated. With enhanced electric field at source side through gate configuration for steeper subthreshold slope (SS), the device with self-depleted structure can effectively suppress the leakage current and simultaneously achieve the dominant Schottky barrier tunneling current for high ON-current without area penalty, which can alleviate the problems in silicon TFET. In addition, the proposed TSB-TFET can have comparable DIBL effect and reduced gate-to-drain capacitance compared with traditional TFET. Further device optimization is experimentally achieved by extended multi-finger gate configuration of the same footprint and barrier modulation by dopant segregation Schottky technology. With compatible bulk CMOS technology, the fabricated device can achieve steep SS over almost 5 decades of current, as well as high I ON /I OFF ratio (~10 7 ). The proposed device with high compatibility is very promising for future low power system applications.
In order to improve the HKMG interface states density and electrical characteristics, four different interface layers have been studied in this paper. They are 7Aå thickness of SiO2 produced by rapid thermal anne...
In order to improve the HKMG interface states density and electrical characteristics, four different interface layers have been studied in this paper. They are 7Aå thickness of SiO2 produced by rapid thermal annealing process at 1000°C, 4Aå thickness of SiO2 produced by rapid thermal annealing process at 700°C, 10Aå thickness of silicon nitride produced by LPCVD process at 620°C, and 20Aå thickness of SiO2 produced by traditional horizontal furnace process at 830°C. It was found that there were two samples, the interface layers of 7Aå SiO2 and 10Aå silicon nitride, having excellent interface state density (1.5~1.7×1011cm-2ev-1) and gate leakage (3.1~3.5×10-7A). Considering the thinner equivalent oxide thickness (Eot), we choose 10Aå silicon nitride as the best one
This paper presents a novel dynamic element matching (DEM) method called Thermo Data Weighted Average (TDWA) for Nyquist-rate current - steering digital to analog converter (DAC). When the input code changes, it only ...
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This paper presents a novel dynamic element matching (DEM) method called Thermo Data Weighted Average (TDWA) for Nyquist-rate current - steering digital to analog converter (DAC). When the input code changes, it only increase or decrease the number of unit current source which is be chosen. This approach can reach a better static performance than full random DEM technique but also eliminate signal dependent distortions to achieve good linearity at high sampling frequencies as other DEM implementations.
A drive system for active-matrix OLED panel is presented. The developed system comprises a digital interface which can receive DVI or MCU signals directly, a digital control part, a SRAM for storing display informatio...
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A drive system for active-matrix OLED panel is presented. The developed system comprises a digital interface which can receive DVI or MCU signals directly, a digital control part, a SRAM for storing display information, common drivers, and the 64-step gray scale segment drivers. Both common driver and segment driver is capable to be cascaded, so it can drive panels in different resolutions by using multiple chips. The drivers are using 0.35 um CMOS technology with 15V high voltage devices.
This paper proposes a new structure of LED(Light-emitting diode) driver for obtaining a low mismatch output current between different channels and even reduces the chip area. It's fabricated with TSMC 0.35 μm DDD...
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This paper proposes a new structure of LED(Light-emitting diode) driver for obtaining a low mismatch output current between different channels and even reduces the chip area. It's fabricated with TSMC 0.35 μm DDD process. The chip contains 16 channels and the maximum/minimum output current is 3mA/45mA, respectively. The value of each channel's output current is the same and controlled by a programmable 6-bits digital input signals. The circuit uses constant gate voltage of the power MOS working in the linear region whose (V GS - V TH ) is 10 to 50 times of V DS . The advantage is no DAC(Digital-to-Analog Converter) and no complex gate voltage generating circuit. Simple gate voltage generating circuit can also adapt to a wide range of external resistance changes. Because of the lower mismatch caused by threshold voltage mismatch, it can achieve a highly matched output current. The chip has only ±1.1% mismatch between different channels. The area of each channel's power MOS is only 200 μm × 100 μm. The area of analog part including current bias, bandgap reference, current mirror, and other control circuits is only 400 μm × 200 μm.
For interconnect between NoC (Network-on-Chip) routers, power consumption is high and data rates are limited when conventional transceivers are used. In this paper, a novel high-speed and low-power source-synchronous ...
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We demonstrate high performance silicon nanowire gate-all-around MOSFETs (SNWFETs) fabricated on bulk Si by a novel top-down CMOS-compatible method. The fabricated N- and P-type SNWFETs of sub-50 nm gate length and of...
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We demonstrate high performance silicon nanowire gate-all-around MOSFETs (SNWFETs) fabricated on bulk Si by a novel top-down CMOS-compatible method. The fabricated N- and P-type SNWFETs of sub-50 nm gate length and of ~5 nm in diameter show excellent short channel effects (SCEs) immunity with subthreshold slope (SS) of 90/69 mV/dec, DIBL of 47/10 mV/V, and high driving current of 2×10 3 /5.4×10 3 μA/μm at 0.1 nA/μm off-current.
Modern electronic circuit requires compact,multifunctional technology in communication ***,it is very difficult due to the limitations in passive component miniaturization and the complication of fabrication *** bandp...
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Modern electronic circuit requires compact,multifunctional technology in communication ***,it is very difficult due to the limitations in passive component miniaturization and the complication of fabrication *** bandpass filter is one of the most important passive components in millimeter(mm)-wave communication system,attracting significant interest in three-dimension(3D) miniaturized design,which is few *** this paper,a bandpass filter structure using low-temperature co-fired ceramic(LTCC) technology,which is fully integrated in a system-in package(SIP) communication module,is presented for miniaturized and high reliable mm-wave *** bandpass filter with 3D end-coupled microstrip resonators is implemented in order to achieve a high performance bandwidth ***,all of the resonators are embedded into different ceramic layers to decrease the insertion loss and enhance the out-of-band rejection performance by optimizing the coupling coefficient and the coupling strength.A fence structure,which is formed by metal-filled via array with the gap less than quarter wavelength,is placed around the embedded bandpass filter to avoid electromagnetic(EM) interference problem in multilayer *** structural model is validated through actual LTCC *** bandpass filter is successfully manufactured by modifying the co-fireablity characteristics,adjusting the sintering profile,releasing the interfacial stress,and reducing the shrinkage mismatch with different *** results show good performance and agree well with the high frequency EM full wave *** influence of layer thickness and dielectric constant on the frequency response in fabricated process is analyzed,where thicker ceramic sheets let the filter response shift to higher ***,measured S-parameters denote the center frequency is also strongly influenced by the variation of ceramic material's dielectric *** an
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