A two-probe system of the heterojunction formed by an (8, 0) carbon nanotube (CNT) and an (8, 0) silicon carbide nanotube (SiCNT) was established based on its optimized structure. By using a method combining n...
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A two-probe system of the heterojunction formed by an (8, 0) carbon nanotube (CNT) and an (8, 0) silicon carbide nanotube (SiCNT) was established based on its optimized structure. By using a method combining nonequilibrium Green's function (NEGF) with density functional theory (DFF), the transport properties of the het-erojunction were investigated. Our study reveals that the highest occupied molecular orbital (HOMO) has a higher electron density on the CNT section and the lowest unoccupied molecular orbital (LUMO) mainly concentrates on the interface and the SiCNT section. The positive and negative threshold voltages are +1.8 and -2.2 V, respectively.
Fine silica-like lines with 11 nm width are successfully fabricated using x-ray Fresnel diffraction exposure. X-rays pass a mask of 175-nm-wide lines and 125-nm-wide spaces and form sharp peaks on a wafer coated with ...
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Fine silica-like lines with 11 nm width are successfully fabricated using x-ray Fresnel diffraction exposure. X-rays pass a mask of 175-nm-wide lines and 125-nm-wide spaces and form sharp peaks on a wafer coated with a layer of hydrogen silsesquioxane resist (HSQ). By precisely controlling the mask-wafer gap at 10 μm using the laser interferogram method, the fine structures are defined on HSQ. Experimental images are reproduced by a simulation using the one-dimensional beam propagation method. This lithographic technique presents a novel and convenient way to fabricate fine silica-like structures and devices in nano-optical and nanoelectronic applications.
For the radial boundary force induced in the process, the strain energy distribution and strain tensor components in Ge (110) nanowire (NW) are calculated by finite element method. Based on the strain distribution, we...
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This article presents a method for designing and fabricating a surface acoustic wave (SAW) delay line for chemical-agent sensors. To improve the frequency stability and detection sensitivity, the authors designed and ...
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A novel organic memory device based on titany 1 phthalocyanine (TiOPc) thin film sandwiched between Aluminum and indium tin oxide electrodes was reported. With a single-component organic material, the device can achie...
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Arrays of low-dimensional molecular crystals of square columns(1-D)and nanolamellae(2-D)of Zn[TCNQ]_(2)(H_(2)O)_(2)with large areas(up to 1020 cm^(2))have been synthesized by controlled addition of water to Zn and ***...
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Arrays of low-dimensional molecular crystals of square columns(1-D)and nanolamellae(2-D)of Zn[TCNQ]_(2)(H_(2)O)_(2)with large areas(up to 1020 cm^(2))have been synthesized by controlled addition of water to Zn and *** on the ability to accurately control the reaction,a new moisture and water indicator has been *** simple method,the large areas of material prepared,the fine size tuning,and the typical semiconductor behavior of the resulting low-dimensional molecular materials promise applications in molecular electronics as well as *** system is an effective indicator for the detection of traces of water and moisture.
This paper proposes a ZSCTS methodology aiding in zero skew clock tree synthesis suitable to the mainstream industry clock tree synthesis (CTS) design flow. At the gate level, the original clock net is broken up into ...
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This paper proposes a ZSCTS methodology aiding in zero skew clock tree synthesis suitable to the mainstream industry clock tree synthesis (CTS) design flow. At the gate level, the original clock net is broken up into smaller partitions, and the clock buffers are inserted as pseudo clock sources to drive each portion. The automatic place and route (APR) tool may synthesize each clock subtree with better performance. The proposed methodology is applied to a chip level clock tree network and achieves good results.
This paper proposes a method aiding in low clock skew applicable to the mainstream industry clock tree synthesis (CTS) design flow. The original clock root is partitioned into several pseudo clock sources at the gate ...
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This paper proposes a method aiding in low clock skew applicable to the mainstream industry clock tree synthesis (CTS) design flow. The original clock root is partitioned into several pseudo clock sources at the gate level. The automatic place and route (APR) tool may synthesize the clock tree with better performance in clock skew because each pseudo clock source drives smaller number of fan out. The proposed method is applied to a chip level clock tree network and achieves good results.
Dynamic circuit is suitable for high-speed application, but often suffers from noise related reliability problems which become increasingly prominent as the technology are entering into the scores of nano meter era. T...
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Dynamic circuit is suitable for high-speed application, but often suffers from noise related reliability problems which become increasingly prominent as the technology are entering into the scores of nano meter era. This paper presented a new dynamic circuit scheme, which could achieve higher noise margin without sacrificing much power consumption and delay time. This design achieves a higher noise margin (1.2 V) by finely tuning the transistor size. The effectiveness of new scheme is demonstrated in both NMOS series and parallel circuits. The simulation result shows that, compared with other published work, the proposed structure has the highest noise margin for the same power-delay product (PDP) 1 .
Pentacene organic field effect transistors with a series of submicrometer channel have been fabricated and characterized. Source and drain metal electrodes was made by electron-beam lithography and lift-off process. I...
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