Silicon nanocrystals synthesized by electron beam co-evaporation (EBCE) of Si and HfO2 mixture are studied. HfO2 and Si powder are uniformly mixed together in certain proportion. The mixed Si & HfO2 powder is evap...
Silicon nanocrystals synthesized by electron beam co-evaporation (EBCE) of Si and HfO2 mixture are studied. HfO2 and Si powder are uniformly mixed together in certain proportion. The mixed Si & HfO2 powder is evaporated by electron beam evaporation technique. Then the SRO thin films are annealed at different temperatures at 2 hours in N2 ambient to synthesize Silicon nanocrystals. For the sample annealed at 1050 ° at 2 hours, silicon nanocrystals with different size between 3 nm to 5 nm, the mean diameter of 4.0 nm, and the density of 3×1012 cm-2 are evidently observed by high resolution transmission electron microscopy (HRTEM). Then the Raman scattering and photoluminescence spectra arising from Silicon nanocrystals are further confirmed the above result. In addition, the samples annealed at 900 ° for 2 hours to 8 hours are carefully studied by Raman spectra. This way of preparing SRO thin films and Si NCs has unique advantage and is controllable and flexible
In this paper,the recovery characteristics of negative bias temperature instability(NBTI) of pMOSFETs under drain bias were *** is observed that,the drain bias not only worsens the NBTI degradation in high |V| regio...
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In this paper,the recovery characteristics of negative bias temperature instability(NBTI) of pMOSFETs under drain bias were *** is observed that,the drain bias not only worsens the NBTI degradation in high |V| region but also suppresses the recovery ratio of *** time evolutions of recovery show that the drain bias dependent NBTI recovery is mainly related to the fast recovery effect in initial ls. While in long time scale,the recovery obeys power law dependence on time.A physical model based on donor-type interface traps neutralization at the beginning of recovery is proposed to explain the suppressed recovery ratio under drain bias.
<正>A voltage doubler,which avoids body effect and then improves rise time and efficiency even with 1V power supply,is *** art is designed for word line boosting,using 0.18um EEPROM *** only the voltage doubler can ...
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<正>A voltage doubler,which avoids body effect and then improves rise time and efficiency even with 1V power supply,is *** art is designed for word line boosting,using 0.18um EEPROM *** only the voltage doubler can work with capacitive load normally,but also it can supply load current and achieve higher *** whole circuit can be implemented on chip and is suitable for low voltage *** addition,theoretical analysis and simulation results have been given.
In this paper, the characteristics and mechanism of the transition metal oxide (TMO) based resistive switching memory (RRAM) devices were addressed. The results show that doping in oxide matrix materials, electrode ma...
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ISBN:
(纸本)9781424421855
In this paper, the characteristics and mechanism of the transition metal oxide (TMO) based resistive switching memory (RRAM) devices were addressed. The results show that doping in oxide matrix materials, electrode material, and operating mode of the set/reset process may significantly affect the resistive switching behaviors of RRAM devices. Optimizing the dopants and matrix materials, electrode materials, device structure, and operating modes and understanding the related mechanisms are required to achieve the excellent device performance of TMO-based RRAM for the memory application. A unified physical model, based on the electron hopping transport between oxygen vacancies along the conductive filament paths, is used to explain and describe the resistive switching behaviors of the TMO based RRAM devices.
The conventional matched filter structures are investigated in this paper,An acquisition circuit based on the polyphase form matched filter in Global Positioning System(GPS) receiver is *** the cost of less hardware r...
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The conventional matched filter structures are investigated in this paper,An acquisition circuit based on the polyphase form matched filter in Global Positioning System(GPS) receiver is *** the cost of less hardware resource,the significant advantage in the speed of synchronization is *** 32×128 polyphase form matched filter,the critical path delay approximately reduces 1/2,the sample frequency would be double.
Intra-die fluctuations in the nanoscale CMOS technology emerge inherently to geometrical variations such as line edge roughness(LER) and oxide thickness fluctuations (OTF).A full 3-D statistical simulation is presente...
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Intra-die fluctuations in the nanoscale CMOS technology emerge inherently to geometrical variations such as line edge roughness(LER) and oxide thickness fluctuations (OTF).A full 3-D statistical simulation is presented to investigate the impact of geometrical variations on the FinFETs *** this work,roughness is introduced by a Fourier analysis of the power spectrum of Gaussian autocorrelation *** influence of different geometrical variation sources is compared and *** results shows that FinFETs performance is most sensitive to the fin LER,which causes a remarkable shift and fluctuations in threshold voltage, drain induced barrier lower effect(DIBL) and leakage current. The impact of gate LER follows that of fin *** simulation also suggests quantum confinement effect accounts for the aggressive fluctuations due to fin LER.
<正>Ⅰ.Introduction Flash memories are one of the basic building blocks of today’s electronic *** floating gate type of Flash memory is impossible to scale down to beyond 45nm due to the difficulty in scaling the t...
<正>Ⅰ.Introduction Flash memories are one of the basic building blocks of today’s electronic *** floating gate type of Flash memory is impossible to scale down to beyond 45nm due to the difficulty in scaling the tunnel oxide and the gate coupling ratio[1].Because of the difficulty in maintaining high gate coupling ratio and preventing cross talk between neighboring cells,NAND technology is forecasted to migrate gradually from floating gate devices(FG) to charge trapping memory(CTM)[2]. CTM are not sensitive to tunnel oxide damage since the charge is stored in discrete traps and one weak spot does
The total dose radiation effect(TDRE) has been regarded as one of the most harmful factors to degrade MOS *** this paper,a simple new method called avalanche injection of holes is introduced to simulate or displace ...
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The total dose radiation effect(TDRE) has been regarded as one of the most harmful factors to degrade MOS *** this paper,a simple new method called avalanche injection of holes is introduced to simulate or displace the radiation experiments to determine the TDRE of MOS *** TDRE, avalanche injection of holes can also provide sufficient holes to flow into the gate oxide layer where a small part of these holes can be trapped in the defects and cause a shift of flat-band voltage(ΔV) of MOS device,we can conclude that the structure which has a greaterΔV would be easier to be affected by TDRE.
3-D mixed-mode device-circuit simulation is presented to investigate stochastic mismatch of FinFETs SRAM cell induced by process variation including fin-thickness and gate length variation as well as fin line edge rou...
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3-D mixed-mode device-circuit simulation is presented to investigate stochastic mismatch of FinFETs SRAM cell induced by process variation including fin-thickness and gate length variation as well as fin line edge roughness (LER). In this work, 20 nm FinFETs SRAMpsilas sensitivity of read and write static noise margin (SNM) to process variation is evaluated. The worst cases of read and write SNM under the influence of process variation are summarized. The results show that FinFETs SRAMpsilas stability is most sensitive to the access transistorpsilas fin-thickness variation. Under the worst cases, increasing the pull-down transistorpsilas fin-number may improve read SNM. The fin LER can cause aggressive fluctuations of the butterfly-curves and impose a big challenge on robust FinFETs SRAM design. Adopting 8T cell instead of 6T cell can alleviate the fin LER effect on read stability.
A multiplexer with a low-distortion high-bandwidth analog switch is presented. The gate-to-source voltage of the switch is set by the combined on-voltage of a pMOS and an nMOS, and the difference between its gate-sour...
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A multiplexer with a low-distortion high-bandwidth analog switch is presented. The gate-to-source voltage of the switch is set by the combined on-voltage of a pMOS and an nMOS, and the difference between its gate-source voltage and the threshold voltage (VGST) is guaranteed to be constant with input variation. Thus, the body effect is nearly canceled. Implemented in a TSMC 0.18 μm CMOS process, results from HSPICE simulation show that the VGST is nearly constant with an input range from 0.3 to 1.7 V, and the -3 dB bandwidth is larger than 10 GHz;the SFDR (spurious free dynamic range) of the output is 67.11 dB with 1 GHz input frequency;the turn-on time is 2.98 ns, and the turn-off time is 1.35 ns, which indicates a break-before-make action of the multiplexer. The proposed structure can be applied to high speed signal transmission.
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