<正>Ⅰ.Introduction Flash memories are one of the basic building blocks of today’s electronic *** floating gate type of Flash memory is impossible to scale down to beyond 45nm due to the difficulty in scaling the t...
<正>Ⅰ.Introduction Flash memories are one of the basic building blocks of today’s electronic *** floating gate type of Flash memory is impossible to scale down to beyond 45nm due to the difficulty in scaling the tunnel oxide and the gate coupling ratio[1].Because of the difficulty in maintaining high gate coupling ratio and preventing cross talk between neighboring cells,NAND technology is forecasted to migrate gradually from floating gate devices(FG) to charge trapping memory(CTM)[2]. CTM are not sensitive to tunnel oxide damage since the charge is stored in discrete traps and one weak spot does
The total dose radiation effect(TDRE) has been regarded as one of the most harmful factors to degrade MOS *** this paper,a simple new method called avalanche injection of holes is introduced to simulate or displace ...
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The total dose radiation effect(TDRE) has been regarded as one of the most harmful factors to degrade MOS *** this paper,a simple new method called avalanche injection of holes is introduced to simulate or displace the radiation experiments to determine the TDRE of MOS *** TDRE, avalanche injection of holes can also provide sufficient holes to flow into the gate oxide layer where a small part of these holes can be trapped in the defects and cause a shift of flat-band voltage(ΔV) of MOS device,we can conclude that the structure which has a greaterΔV would be easier to be affected by TDRE.
3-D mixed-mode device-circuit simulation is presented to investigate stochastic mismatch of FinFETs SRAM cell induced by process variation including fin-thickness and gate length variation as well as fin line edge rou...
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3-D mixed-mode device-circuit simulation is presented to investigate stochastic mismatch of FinFETs SRAM cell induced by process variation including fin-thickness and gate length variation as well as fin line edge roughness (LER). In this work, 20 nm FinFETs SRAMpsilas sensitivity of read and write static noise margin (SNM) to process variation is evaluated. The worst cases of read and write SNM under the influence of process variation are summarized. The results show that FinFETs SRAMpsilas stability is most sensitive to the access transistorpsilas fin-thickness variation. Under the worst cases, increasing the pull-down transistorpsilas fin-number may improve read SNM. The fin LER can cause aggressive fluctuations of the butterfly-curves and impose a big challenge on robust FinFETs SRAM design. Adopting 8T cell instead of 6T cell can alleviate the fin LER effect on read stability.
A multiplexer with a low-distortion high-bandwidth analog switch is presented. The gate-to-source voltage of the switch is set by the combined on-voltage of a pMOS and an nMOS, and the difference between its gate-sour...
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A multiplexer with a low-distortion high-bandwidth analog switch is presented. The gate-to-source voltage of the switch is set by the combined on-voltage of a pMOS and an nMOS, and the difference between its gate-source voltage and the threshold voltage (VGST) is guaranteed to be constant with input variation. Thus, the body effect is nearly canceled. Implemented in a TSMC 0.18 μm CMOS process, results from HSPICE simulation show that the VGST is nearly constant with an input range from 0.3 to 1.7 V, and the -3 dB bandwidth is larger than 10 GHz;the SFDR (spurious free dynamic range) of the output is 67.11 dB with 1 GHz input frequency;the turn-on time is 2.98 ns, and the turn-off time is 1.35 ns, which indicates a break-before-make action of the multiplexer. The proposed structure can be applied to high speed signal transmission.
A buck DC/DC switching regulator is implemented by automatically altering the modulation mode according to the load current that ranges from 0.01 to 3A. The pseudo-PFM mode is applied when duty cycle is less than 20%,...
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A buck DC/DC switching regulator is implemented by automatically altering the modulation mode according to the load current that ranges from 0.01 to 3A. The pseudo-PFM mode is applied when duty cycle is less than 20%, and the PWM mode is selected in a range of duty cycle from 20% to 100%. The average conversion efficiency of the regulator is about 90% when the output current varies. The proposed dual-mode-control die is implemented in a 0.5m DPDM CMOS mixed-signal process and a power p-MOSFET is used in the chip by hybrid integration.
This work studied systemically the device characteristics when the OFETs' channels turn into hundreds of nm. Standard planar OFETs have been fabricated using electronic beam lithography. Copper phthalocyanine is u...
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Low-energy electron beam lithography has a variety of advantages. The traditional electron scattering model consisting of Rutherford elastic scattering cross section and Bethe continuous slowing down approximation for...
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ISBN:
(纸本)9781424421855
Low-energy electron beam lithography has a variety of advantages. The traditional electron scattering model consisting of Rutherford elastic scattering cross section and Bethe continuous slowing down approximation formula are not suitable for low-energy electron beam lithography. A more accurate physical model describing the low-energy electron scattering processes was proposed in this work. And Monte Carlo method was used to simulate the complex scattering processes of Gaussian-distribution low-energy electron beam in the target of thin film on thick substrate. The simulation results show that low-energy electron beam lithography has advantages of high throughput, low proximity effects and small damage to the underlying substrate. It is in agreement with the conclusion got from Lee et al¿s and Peterson et al¿s experiments.
The total dose radiation effect (TDRE) has been regarded as one of the most harmful factors to degrade MOS devices. In this paper, a simple new method called avalanche injection of holes is introduced to simulate or d...
详细信息
ISBN:
(纸本)9781424421855
The total dose radiation effect (TDRE) has been regarded as one of the most harmful factors to degrade MOS devices. In this paper, a simple new method called avalanche injection of holes is introduced to simulate or displace the radiation experiments to determine the TDRE of MOS devices. Like TDRE, avalanche injection of holes can also provide sufficient holes to flow into the gate oxide layer where a small part of these holes can be trapped in the defects and cause a shift of flat-band voltage (¿V FB ) of MOS device, we can conclude that the structure which has a greater ¿V FB would be easier to be affected by TDRE.
A voltage doubler, which avoids body effect and then improves rise time and efficiency even with 1 V power supply, is presented. This art is designed for word line boosting, using 0.18 um EEPROM technology. Not only t...
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ISBN:
(纸本)9781424421855
A voltage doubler, which avoids body effect and then improves rise time and efficiency even with 1 V power supply, is presented. This art is designed for word line boosting, using 0.18 um EEPROM technology. Not only the voltage doubler can work with capacitive load normally, but also it can supply load current and achieve higher efficiency. The whole circuit can be implemented on chip and is suitable for low voltage application. In addition, theoretical analysis and simulation results have been given.
A flexible air-bridge method is proposed that is useful for high temperature microwave devices. This method makes use of different resists to give several resists as a sacrificial layer. After low temperature baking, ...
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A flexible air-bridge method is proposed that is useful for high temperature microwave devices. This method makes use of different resists to give several resists as a sacrificial layer. After low temperature baking, a perfect arch sacrificial layer of bridges with a ratio higher than 60% is obtained. An air-bridge inter-connection structure with excellent characteristics and high reliability can be easily fabricated with this method.
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