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Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors 2008年第10期29卷 1922-1927页

作者： Wang, Huang Sun, Lingling Yu, Zhiping Liu, Jun Key Laboratory of RF Circuits and Systems Hangzhou Dianzi University Hangzhou 310037 China Institute of Microelectronics Tsinghua University Beijing 100084 China

A novel large-signal equivalent circuit model of RF-SOI LDMOS based on Philips MOS Model 20 (MM20) is presented. The weak avalanche effect and the power dissipation caused by self-heating are described. The RF parasitic elements are extracted directly from measured S-parameters with analytical methods. Their final values can be obtained quickly and accurately through the necessary optimization. The model is validated in DC, AC small-signal, and large-signal analyses for an RF-SOI LDMOS of 20-fingers (channel mask length, L = 1m, finger width, W = 50m) gate with high resistivity substrate and body-contact. Excellent agreement is achieved between simulated and measured results for DC, S-parameters (10MHz-20.01GHz), and power characteristics, which shows our model is accurate and reliable. MM20 is improved for RF-SOI LDMOS large-signal applications. This model has been implemented in Verilog-A using the ADS circuit simulator (hpeesofsim).

关键词： Scattering parameters

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Compensation mechanism for semi-insulating 6H-SiC doped with vanadium

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors

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Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors 2008年第2期29卷 206-209页

作者： Wang, Chao Zhang, Yimen Zhang, Yuming Wang, Yuehu Xu, Daqing Key Laboratory for Wide Band-Gap Semiconductor Materials and Devices Microelectronics Institute Xidian University Xi'an 710071 China

A model is presented to describe a compensation mechanism for semi-insulating 6H-SiC grown with the intentional doping of vanadium. Because we found nitrogen to be the principal shallow donor impurity in SiC by secondary ion mass spectroscopy (SIMS) measurements, semi-insulating properties in SiC are achieved by compensating the nitrogen donor with the vanadium deep acceptor level. The presence of different vanadium charge states V3+ and V4+ is detected by electron paramagnetic resonance and optical absorption measurements, which coincides with the results obtained by SIMS measurements. Both optical absorption and low temperature photoluminescence measurements reveal that the vanadium acceptor level is located at 0.62eV below the conduction band in 6H-SiC.

关键词： Silicon carbide

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An enhancement-mode AlGaN/GaN HEMT with recessed-gate

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors

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Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors 2008年第9期29卷 1682-1685页

作者： Wang, Chong Zhang, Jinfeng Quan, Si Hao, Yue Zhang, Jincheng Ma, Xiaohua Key Laboratory of Wide Band Gap Semiconductor Materials and Devices Institute of Microelectronics Xidian University Xi'an 710071 China

Fabrication of enhancement-mode high electron mobility transistors on AlGaN/GaN heterostructures grown on sapphire substrates is reported. These devices with 1.2m gate-length, 4 mm space between source and drain, and 15 nm recessed-gate depth exhibit a maximum drain current of 332 mA/mm at 3V, a maximum transconductance of 221 mS/mm, a threshold voltage of 0.57V, ft of 5.2GHz, and fmax of 9.3GHz. A dielectric layer formed unintentionally during recessed-gate etching is confirmed by contrasting the Schottky I-V characteristics of pre-etching and post-etching. The frequency characteristics and subthreshold characteristics of the devices are studied in detail.

关键词： Threshold voltage

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Deep level transient Fourier spectroscopy and photoluminescence of vanadium acceptor level in n-type 4H-SiC

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors

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Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors 2008年第2期29卷 240-243页

作者： Wang, Chao Zhang, Yimen Zhang, Yuming Wang, Yuehu Xu, Daqing Key Laboratory for Wide Band-Gap Semiconductor Materials and Devices Institute of Microelectronics Xidian University Xi'an 710071 China

Deep level transient Fourier spectroscopy (DLTFS) measurements are used to characterize the deep impurity levels in n-type 4H-SiC by vanadium ions implantation. Two acceptor levels of vanadium at Ec-0.81 and Ec-1.02eV with the electron capture cross section of 7.0 × 10-16 and 6.0 × 10-16 cm2 are observed, respectively. Low-temperature photoluminescence measurements in the range of 1.4-3.4eV are also performed on the sample, which reveals the formation of two electron traps at 0.80 and 1.16eV below the conduction band. These traps indicate that vanadium doping leads to the formation of two deep acceptor levels in 4H-SiC, with the location of 0.8±0.01 and 1.1±0.08eV below the conduction band.

关键词： Silicon carbide

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Analysis of property of HSQ in electron beam lithography

Analysis of property of HSQ in electron beam lithography

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Quantum Optics, Optical Data Storage, and Advanced Microlithography

作者： Zhao, Min Zhu, XiaoLi Chen, Baoqin Niu, Jiebin Liu, Ming Xie, Changqing Key Laboratory of Nano-fabrication and Novel Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences NO.3 Bei-Tu-Cheng West Road Beijing 100029 China

ISBN: (纸本)9780819470027

Hydrogen silsesquioxane (HSQ) is a kind of inorganic negative-tone resist for electron beam lithography with high pattern resolution of about 5 nm. It is a kind of promising resist used in fabrication of nanostructures such as transmission grating (TG), dots array, and chiral structures. But the poor sensitivity limits the extensive application of HSQ. And the property of HSQ in electron beam lithography is also studied little before. In this paper, from the viewpoint of chemical structure the property of HSQ in electron beam lithography has been proposed and experiments have also been presented with the variety of the exposure dose and development conditions. It is proved by experiments not only the sensitivity and contrast of HSQ but also the influence of proximity effect can be modulated by changing the baking temperature and concentration of developer with the same exposure conditions. 100 nm lines at 200 nm pitch grating patterns with excellent vertical side-wall and line-edge roughness have been achieved in more than 450 nm thickness HSQ layer by increasing the concentration of developer and reducing the baking temperature in combination with optimization of exposure conditions.

关键词： Photoresists

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Development and characteristic analysis of MOS AlGaN/GaN HEMTs

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors

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Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors 2008年第8期29卷 1557-1560页

作者： Wang, Chong Yue, Yuanzheng Ma, Xiaohua Hao, Yue Feng, Qian Zhang, Jincheng Key Laboratory of Wide Band Gap Semiconductor Materials and Devices Institute of Microelectronics Xidian University Xi'an 710071 China

The fabrication of MOS high electron mobility transistors on AlGaN/GaN heterostructures grown on sapphire substrates is reported. The gate-length is 1 m and the distance between the source and drain is 4 m. The 4 nm SiO2 dielectric is evaporated by electron beam. These devices exhibit a maximum drain current of 718 mA/mm at 4V, a maximum transconductance of 172 mS/mm, an ft of 8.1GHz, and an fmax of 15.3GHz. The gate leakage current of the MOS HEMT is 2 orders lower than a Schottky gate HEMT. The thin SiO2 dielectric between gate and semiconductor is used to ensure the reduction of gate leakage current and to ensure the trans-conductance of the devices is not impacted.

关键词： High electron mobility transistors

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A double high-voltage p-LDMOS and its compatible process for PDP scan-driver ICs

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors

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Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors 2008年第9期29卷 1758-1763页

作者： Li, Xiaoming Zhuang, Yiqi Zhang, Li Xin, Weiping Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices Microelectronics Institute Xidian University Xi'an 710071 China

A high-voltage p-LDMOS (HV-pMOS) with field-oxide as gate dielectric and a RESURF drain drift region to undertake high gate-source voltage and drain-source voltage for the scan driver chip of plasma display panels (PDP) is purposed based on the epitaxial bipolar-CMOS-DMOS (BCD) process. The key considerations and parameters of the design are discussed: The thickness of gate dielectrics is 1 mm and the area of the device is 80m × 80m. Only 18 photoetch-ing steps are needed in the developed process, which is compatible with standard CMOS, bipolar, and VDMOS devices. The breakdown voltage of the HV-pMOS in the process control module (PCM) is more than 200V. The results are favorable for 170V PDP scan driver chips, which contribute to the competitive cost efficiency.

关键词： Gate dielectrics

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Simulation of charge trapping memory with novel structures

Simulation of charge trapping memory with novel structures

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International Conference on Solid-State and Integrated Circuit Technology

作者： X. Y. Liu Y. C. Song Gang Du R.Q. Han Z. L. Xia D. Kim K.-H. Lee Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China Samsung Electronics Company Limited South Korea

The floating gate type of flash memory is impossible to scale down to beyond 45 nm due to the difficulty in scaling the tunnel oxide and the gate coupling ratio. Because of the difficulty in maintaining high gate coupling ratio and preventing cross talk between neighboring cells, NAND technology is forecasted to migrate gradually from floating gate devices (FG) to charge trapping memory (CTM). CTM are not sensitive to tunnel oxide damage since the charge is stored in discrete traps and one weak spot does not cause all stored charge to leak out as in floating gate devices. The NAND HC-TANOS flash cell has been generated in three dimensional TCAD tools with 38 nm gate length, 34 nm channel width and charge trapping structures. A structure of Al 2 O 3 (15 nm)/Si 3 Na (6.5 nm)/SiO 2 (4.5 nm) with TaN gate was employed as the gate stack. To study the effects of gate stack coverage on flash cell's performance, the shape of gate stack is varied while keeping all other structural parameters fixed.

关键词： Tunneling Shape Circuit simulation Electron traps Nonvolatile memory microelectronics Flash memory Poisson equations Failure analysis Laboratories

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Electrical resistive switching in organic molecules and high-k dielectric bi-layer films

Electrical resistive switching in organic molecules and high...

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7th International Conference on Semiconductor Technology, ISTC 2008

作者： Tu, Deyu Liu, Ming Shang, Liwei Liu, Xinghua Xie, Changqing Key Laboratory of Nano-Fabrication and Novel Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences No. 3 West Road of North Tucheng Chaoyang District Beijing 100029 China

ISBN: (纸本)9789881740816

Molecular electronics provides an alternative way to scale the dimension of electronic devices down to several nanometers, with the advantages of low cost, simplicity, and designable electrical properties. Electrical bistable properties through resistive switching are inherently promising for nonvolatile memory as well as information recording. Among these various materials with electrical bistability, monolayer of molecules by Langmuir-Blodgett (LB) deposition or self-assembly offers the best potential to scale down to molecular size. Electrical switching characteristics of eicosanoic acid (EA) monolayer/ high-k dielectric(zirconium oxide, ZrO2/hafnium oxide, HfO 2) bi-layer films were investigated in this paper. The devices with sandwich structure of aluminum (Al)/EA monolayer/high-k dielectric/gold (Au) exhibited electrical bistable behaviors with rectifying effect through resistive switching. Reversible and reproducible bistable switching properties were observed by applying some certain voltage. The bistable behaviors are proposed to be contributed by high-k dielectric layer. This work paves the way for nonvolatile crossbar molecular memory.

关键词： Monolayers

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Recovery characteristics of NBTI of pMOSFETs with oxynitride dielectrics under drain bias

Recovery characteristics of NBTI of pMOSFETs with oxynitride...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Jiaqi Yang Junyan Pan Lihua Huang Xiaoyan Liu Ruqi Han Jinfeng Kang L. F. Zhang Z. W. Zhu C. C. Liao H. M. Wu Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China Semiconductor Manufacturing International Corporation Shanghai China

ISBN: (纸本)9781424421855

In this paper, the recovery characteristics of negative bias temperature instability (NBTI) of pMOSFETs under drain bias were studied. It is observed that, the drain bias not only worsens the NBTI degradation in high |V ds | region but also suppresses the recovery ratio of NBTI. The time evolutions of recovery show that the drain bias dependent NBTI recovery is mainly related to the fast recovery effect in initial 1s. While in long time scale, the recovery obeys power law dependence on time. A physical model based on donor-type interface traps neutralization at the beginning of recovery is proposed to explain the suppressed recovery ratio under drain bias.

关键词： Niobium compounds Titanium compounds MOSFETs Degradation Stress measurement Phase measurement Dielectric measurements microelectronics circuits Negative bias temperature instability

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