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Technique of mask optimization for achieving the maximal effective litho-CPW

Optics Express 2025年第12期33卷 25783-25797页

作者： Jiashuo Wang Hao Shen Xiaojing Su Wei Zhao Lisong Dong Yajuan Su Yayi Wei State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China University of Chinese Academy of Sciences Beijing 100049 China suxiaojing@*** weiyayi@***

Achieving a large lithography process window (PW) via computational lithography is a crucial prerequisite for ensuring adequate product yield in advanced-node integrated-circuit manufacturing technologies. However, as the critical dimensions of patterns continue to shrink, a chip-level qualified common process window (CPW) necessitates multiple rounds of highly time-consuming iterations of source mask co-optimization (SMO). To ensure a sufficient CPW for yield improvement while reducing the iterations of SMO, this paper presents what we believe to be a novel mask optimization (MO) approach aimed at attaining the maximum effective CPW in every iteration. First, an optimized light source is acquired through SMO and then utilized in subsequent CPW-friendly MO steps. After optimizing all the individual mask patterns, the optimal exposure dose and anchor pattern corresponding to the maximum effective CPW are corrected. Finally, the cost function for MO is updated, and the CPW-friendly MO is executed to ultimately achieve the maximal effective CPW. In the experimental cases studied in this paper, the proposed MO technique, which incorporates corrections for exposure dose, anchor pattern, and cost functions, achieves an 8.79% improvement in CPW compared to the scenario where only mask patterns are considered during MO. The inefficiency caused by the repeated re-optimization of SMO due to insufficient CPW in each iteration is the bottleneck of the source optimization and determination process. This method can further automate the update of the MO process, achieving the maximum CPW result in each MO iteration, significantly shortening the turnaround time of the SMO-MO full procedure, and further increasing full-chip CPW.

关键词： Fourier transforms Imaging systems Light sources Lithography Optical systems Projection systems

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A Broadband Amplifier with Low Group Delay Variation Implemented 9

A Broadband Amplifier with Low Group Delay Variation Impleme...

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9th IEEE MTT-S International Wireless Symposium, IWS 2022

作者： Wang, Yuchen Yuan, Tingting Liu, Guoguo Zhou, Jiuding Liu, Wenliang Lu, Yang Ma, Xiaohua Hao, Yue Xidian University Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices Xian China The Institute of Microelectronics of the Chinese Academy of Sciences Beijing China

ISBN: (数字)9781665481977

ISBN: (纸本)9781665481977

In this paper, a DC to 40 GHz distributed amplifier (DA) employing the negative group delay technique has been successfully implemented using 0.15μm GaAs pHEMT process. It is shown that stagger-tuning negative group delay circuits can be realized in each gain cell of DA. This paper presents a significant improvement in low group delay variation compared to conventional DAs. The proposed DA provides a 15 dB average gain, 3 dB noise figure, and 8ps group delay variation which was validated through theoretical analysis and experimental results. © 2022 IEEE.

关键词： Group delay

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Impact of symmetric gate-recess length on the DC and RF characteristics of InP HEMTs

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Chinese Physics B 2022年第1期31卷 675-679页

作者： Ruize Feng Bo Wang Shurui Cao Tong Liu Yongbo Su Wuchang Ding Peng Ding Zhi Jin High-Frequency High-Voltage Device and Integrated Circuits Center Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China University of Chinese Academy of Sciences Beijing 100029China Guangxi Key Laboratory of Precision Navigation Technology and Application Guilin University of Electronic TechnologyGuilin 541004China

We fabricated a set of symmetric gate-recess devices with gate length of 70 *** kept the source-to-drain spacing(L_(SD))unchanged,and obtained a group of devices with gate-recess length(L_(recess))from 0.4µm to 0.8µm through process *** order to suppress the influence of the kink effect,we have done SiN_(X) passivation *** maximum saturation current density(ID_(max))and maximum transconductance(g_(m,max))increase as L_(recess) decreases to 0.4µ*** this time,the device shows ID_(max)=749.6 mA/mm at V_(GS)=0.2 V,V_(DS)=1.5 V,and g_(m,max)=1111 mS/mm at V_(GS)=−0.35 V,V_(DS)=1.5 ***,as L_(recess) increases,it causes parasitic capacitance C_(gd) and g_(d) to decrease,making f_(max) drastically *** L_(recess)=0.8µm,the device shows f_(T)=188 GHz and f_(max)=1112 GHz.

关键词： InP HEMT InGaAs/InAlAs current gain cut-off frequency(fT) maximum oscillation frequency(f_(max)) gate-recess length(L_(recess))

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An End-to-End SoC for Brain-Inspired CNN-SNN Hybrid Applications

An End-to-End SoC for Brain-Inspired CNN-SNN Hybrid Applicat...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Zhaotong Zhang Yi Zhong Yingying Cui Yawei Ding Yukun Xue Qibin Li Ruining Yang Jian Cao Yuan Wang Key Laboratory of Microelectronic Devices and Circuits (MoE) MPW Center School of Integrated Circuits Peking University School of Software and Microelectronics Peking University Beijing China Beijing Advanced Innovation Center for Integrated Circuits Beijing China

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

Inspired by the brain, Spiking Neural Network (SNN) applies temporally sparse spiking communication to gain more bio-mimetic and highly energy efficient computing. The current mainstream platforms for SNN applications are typically the combination of Host+FPGA+Chip Array, which requires an efficient host to preprocess and encode data. It’s not suitable for end-to-end tasks in edge due to its high system power consumption of host and non-negligible high latency of protocol conversion on FPGA. In addition, Convolutional Neural Network (CNN), exhibits strong feature extraction capabilities. Like the brain's visual system, a hierarchical CNN-SNN hybrid network, in which SNN can make use of CNN’s feature extraction capabilities during encoding, can achieve better performance. In this study, we design a 64Neural-Core Array and integrate it with a CNN encoder and a low-power RISC-V CPU within a System-on-Chip (SoC) to enable comprehensive end-to-end hybrid network application support. The proposed heterogeneous SoC is implemented on a Virtex UltraScale+ XCVU9P FPGA, featuring 32.8K neurons, 37.7M synapses and 578GOPS/s peak performance. It processes MNIST classification with a peak throughput of 2022 images per second at frequency of 250MHz. This design gains a balance between high throughput and recognition accuracy simultaneously.

关键词： Accuracy Visual systems Feature extraction Throughput Encoding System-on-chip Convolutional neural networks

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Impact of gate offset in gate recess on DC and RF performance of InAlAs/InGaAs InP-based HEMTs

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Chinese Physics B 2022年第5期31卷 720-724页

作者： Shurui Cao Ruize Feng Bo Wang Tong Liu Peng Ding Zhi Jin High-Frequency High-Voltage Device and Integrated Circuits Center Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China University of Chinese Academy of Sciences Beijing 100029China Guangxi Key Laboratory of Precision Navigation Technology and Application Guilin University of Electronic TechnologyGuilin 541004China

A set of 100-nm gate-length In P-based high electron mobility transistors(HEMTs)were designed and fabricated with different gate offsets in gate recess.A novel technology was proposed for independent definition of gate recess and T-shaped gate by electron beam *** and RF measurement was *** the gate offset varying from drain side to source side,the maximum drain current(I_(ds,max))and transconductance(g_(m,max))*** the meantime,fTdecreased while f;increased,and the highest fmax of 1096 GHz was *** can be explained by the increase of gate-source capacitance and the decrease of gate-drain capacitance and source *** conductance was also suppressed by gate offset toward source *** provides simple and flexible device parameter selection for HEMTs of different usages.

关键词： InP HEMT InGaAs/InAlAs cut-off frequency(fT) maximum oscillation frequency(fmax) asymmetric gate recess

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Vertical Channel-All-Around (CAA) IGZO FET with Recessed Source/Drain Structure to Improve Contact Characteristics

IEEE Electron Device Letters

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IEEE Electron Device Letters 2025年

作者： Chen, Chuanke Gu, Chen Zhao, Yue Duan, Xinlv Lu, Congyan Niu, Jiebin Zhang, Kaiping Liu, Yu Zhao, Shengjie Li, Weiwei Wu, Wanming Zhang, Chunyu Hu, Ke Wang, Shipeng Tong, Qingding Tang, Yinzhi Lu, Nianduan Geng, Di Li, Ling Institute of Microelectronics of Chinese Academy of Sciences State Key Laboratory of Fabrication Technologies for Integrated Circuits Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China

We proposed recessed source/drain(S/D) structure for vertical channel-all-around (CAA) IGZO FET to introduce contact interlayer and improve its contact characteristics. The IZO interlayer introduced between S/D and IGZO helps to reduce the contact resistance, and boosting the performance of CAA IGZO FET. The fabricated CAA IGZO FETs with 8 nm IZO interlayer show an average Ion @ Vth+1V of 32.6 μA/μm, SS of 86 mV/dec, and Vth of - 0.06 V. The Schottky barrier height qB is extracted to be reduced from 170 meV to 65 meV by introducing the contact interlayer, which confirms the improvement of contact characteristics. © 1980-2012 IEEE.

关键词： Schottky barrier diodes

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In-materio reservoir computing based on nanowire networks:fundamental,progress,and perspective

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Materials Futures 2023年第2期2卷 79-93页

作者： Renrui Fang Woyu Zhang Kuan Ren Peiwen Zhang Xiaoxin Xu Zhongrui Wang Dashan Shang State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of Chinese Academy of SciencesBeijing 100029People’s Republic of China Department of Electrical and Electronic Engineering The University of Hong KongHong Kong 999077People’s Republic of China University of Chinese Academy of Sciences Beijing 100049People’s Republic of China

The reservoir computing(RC)system,known for its ability to seamlessly integrate memory and computing functions,is considered as a promising solution to meet the high demands for time and energy-efficient computing in the current big data landscape,compared with traditional silicon-based computing systems that have a noticeable disadvantage of separate storage and *** review focuses on in-materio RC based on nanowire networks(NWs)from the perspective of materials,extending to reservoir devices and *** common methods used in preparing nanowires-based reservoirs,including the synthesis of nanowires and the construction of networks,are firstly systematically *** physical principles of memristive and memcapacitive junctions are then ***,the dynamic characteristics of nanowires-based reservoirs and their computing capability,as well as the neuromorphic applications of NWs-based RC systems in recognition,classification,and forecasting tasks,are explicated in ***,the current challenges and future opportunities facing NWs-based RC are highlighted,aiming to provide guidance for further research.

关键词： reservoir computing nanowire networks short-term memory dynamic characteristics neuromorphic computing

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Revealing the dynamics of the alloying and segregation of Pt-Co nanoparticles via in-situ environmental transmission electron microscopy

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Nano Research 2023年第2期16卷 3055-3062页

作者： Xing Li Shaobo Cheng Yanghua He Lixiang Qian Dmitri Zakharov Gang Wu Chongxin Shan Liang Zhang Dong Su Henan Key Laboratory of Diamond Optoelectronic Materials and Devices Key Laboratory of Material PhysicsSchool of Physics and MicroelectronicsZhengzhou UniversityZhengzhou 450052China Center for Functional Nanomaterials Brookhaven National LaboratoryUptonNY 11973USA Department of Chemical and Biological Engineering University at BuffaloThe State University of New YorkBuffaloNY 14260USA Center for Combustion Energy School of Vehicle and MobilityTsinghua UniversityBeijing 100084China Beijing National Laboratory for Condensed Matter Physics Institute of PhysicsChinese Academy of SciencesBeijing 100190China

Thermal treatment is a general and efficient way to synthesize intermetallic catalysts and may involve complicated physical *** far,the mechanisms leading to the size and composition heterogeneity,as well as the phase segregation behavior in Pt-Co nanoparticles(NPs)are still not well *** in-situ environmental transmission electron microscopy,the formation dynamics and segregation behaviors of Pt-Co alloyed NPs during the thermal treatment were *** is found that Pt-Co NPs on zeolitic imidazolate frameworks-67-derived nanocarbon(NC)are formed consecutively through both particle migration coalescence and the Ostwald ripening *** existence of Pt NPs is found to affect the movement of Co NPs during their *** the help of theoretical calculations,the correlations between the composition and migration of the Pt and Co during the ripening process were *** complex alloying processes are revealed as key factors leading to the heterogeneity of the synthesized Pt-Co alloyed *** oxidation environment,the Pt-Co NPs become surface faceted gradually,which can be attributed to the oxygen facilitated relatively higher segregation rate of Co from the(111)*** work advances the fundamental understanding of design,synthesis,and durability of the Pt-based nanocatalysts.

关键词： intermetallic catalyst alloying ripening segregation dynamics environmental transmission electron microscopy(ETEM)

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Modeling the Charging Effect on the Twisting Defects During High Aspect Ratio Etching of Dielectrics

Modeling the Charging Effect on the Twisting Defects During ...

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China Semiconductor Technology International Conference (CSTIC)

作者： Yuxuan Zhai Ziyi Hu Junjie Li Rui Chen State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798331513351

ISBN: (纸本)9798331513368

In high-aspect-ratio (HAR) plasma etching of dielectrics, random twisting is frequently observed. The charging effect is considered a potential factor influencing this twisting. We develop a novel model that takes into account the charging effect to simulate the profile evolution of SiO 2 layers and potential distribution during nanoscale HAR etching. The model also explores the effect of charging effect on twisting defects.

关键词： Silicon compounds Integrated circuits Electric potential Monte Carlo methods Simulation Ions Etching Nanoscale devices Dielectrics Plasmas

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A Fully BEOL-Compatible (300°C Annealing) IGZO FeFET with Ultra-High Memory Window (10V) and Prominent Endurance (109)

A Fully BEOL-Compatible (300°C Annealing) IGZO FeFET with U...

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International Electron devices Meeting (IEDM)

作者： Pan Xu Pengfei Jiang Yang Yang Xueyang Peng Wei Wei Tiancheng Gong Yuan Wang Xiao Long Jiebin Niu Zhongguang Xu Chenxin Zhu Zhenhua Wu Qing Luo Ming Liu Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China University of Science and Technology of China Hefei Anhui China

ISBN: (数字)9798350365429

ISBN: (纸本)9798350365436

HfO 2 -based FeFET paves the way for the next generation NVM thecnology, however, demands for high memory window (MW) and roubust reliability (especially the endurance) cannot be combined in the current reported devices, and the contradiction of high MW and low thermal budget (aiming for BEOL compatibility) also needs to be solved. In this work, we propose an integrated ferroelectric (FE) Hf 0.5 Zr 0.5 O 2 (HZO) and amorphous In-Ga-Zn-O (a-IGZO) channel FeFET with a maximum 10V MW and prominent endurance up to 10 9 . Workfunction (WF) engineering is utilized to regualte the intrinsic $\mathrm{V}_{\mathrm{t}}$ to improve the PGM/ERS efficiency with full-loop polarization switching, and the adopted Mo gate can effectively reduce the thermal budget to 300°C ensuring a fully BEOL compatibility. Then with O 3 -plasma treatment to the gate electrode, the introduced tunneling layer can futher improve the MW by gate charge injection. The demonstrated FeFET shows great 3-bit/cell storage ability without states overlapping, high $\mathrm{I}_{\text{on}}/\mathrm{I}_{\text{off}}$ ratio $(>10^{7})$ , as well as great linearity and high $\mathrm{G}_{\max}/\mathrm{G}_{\min}$ (286) during synaptic weight modulation.

关键词： Performance evaluation Nonvolatile memory Thermal engineering Modulation Switches Logic gates Tunneling Reliability FeFETs Next generation networking

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