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Heavy ion energy influence on multiple-cell upsets in small sensitive volumes:from standard to high energies

Nuclear Science and Techniques 2024年第5期35卷 109-121页

作者： Yang Jiao Li-Hua Mo Jin-Hu Yang Yu-Zhu Liu Ya-Nan Yin Liang Wang Qi-Yu Chen Xiao-Yu Yan Shi-Wei Zhao Bo Li You-Mei Sun Pei-Xiong Zhao Jie Liu Institute of Modern Physics Chinese Academy of ScienceLanzhou 730000China University of Chinese Academy of Science Beijing 100049China Spallation Neutron Source Science Center Dongguan 523803China China Electronics Technology Group Corporation No.58 Research Institute Wuxi 214000China Beijing Microelectronics Technology Institute Beijing 100084China Institute of Microelectronics Chinese Academy of SciencesBeijing 100029China Key Laboratory of Science and Technology on Silicon Devices Chinese Academy of SciencesBeijing 100029China

The 28 nm process has a high cost-performance ratio and has gradually become the standard for the field of radiation-hardened ***,owing to the minimum physical gate length of only 35 nm,the physical area of a standard 6T SRAM unit is approximately 0.16μm^(2),resulting in a significant enhancement of multi-cell charge-sharing ***-cell upsets(MCUs)have become the primary physical mechanism behind single-event upsets(SEUs)in advanced nanometer node *** range of ionization track effects increases with higher ion energies,and spacecraft in orbit primarily experience SEUs caused by high-energy ***,ground accelerator experiments have mainly obtained low-energy ion irradiation ***,the impact of ion energy on the SEU cross section,charge collection mechanisms,and MCU patterns and quantities in advanced nanometer devices remains *** this study,based on the experimental platform of the Heavy Ion Research Facility in Lanzhou,low-and high-energy heavy-ion beams were used to study the SEUs of 28 nm SRAM *** influence of ion energy on the charge collection processes of small-sensitive-volume devices,MCU patterns,and upset cross sections was obtained,and the applicable range of the inverse cosine law was *** findings of this study are an important guide for the accurate evaluation of SEUs in advanced nanometer devices and for the development of radiation-hardening techniques.

关键词： 28 nm static random access memory(SRAM) Energy effects Heavy ion Multiple-cell upset(MCU) Charge collection Inverse cosine law

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Fatigue of ferroelectric field effect transistor: mechanisms and optimization strategies

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Journal of Semiconductors 2025年第6期46卷 66-78页

作者： Yu Song Pengfei Jiang Pan Xu Xueyang Peng Qianqian Wei Qingyi Yan Wei Wei Yuan Wang Xiao Long Tiancheng Gong Yang Yang Eskilla Venkata Ramana Qing Luo Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of SciencesBeijing 100029China Laboratory of Microelectronics Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China University of Chinese Academy of Sciences Beijing 101408China I3N-Aveiro Department of PhysicsUniversity of AveiroAveiro3810193Portugal

The novel HfO2-based ferroelectric field effect transistor(FeFET)is considered a promising candidate for next-genera-tion nonvolatile memory(NVM).However,a series of reliability issues caused by the fatigue effect hinder its further ***,a comprehensive understanding of the fatigue mechanisms of the device and optimization strategies is essen-tial for its *** fundamental mechanism of the fatigue effect is attributed to charge trapping and trap generation based on the current studies,and the underlying causes,occurrence locations and specific impacts are analyzed in this *** particular,the asymmetric trapping/detrapping of electrons and holes,as well as the relationship between the ferroelectric(FE)polarization and charge trapping,are given particular *** categorizing and summarizing the current progress,we propose a series of optimization strategies derived based on the fatigue mechanisms.

关键词： FeFET fatigue charge trapping trap generation

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A Comparative study on Total Ionizing Dose Effects of 100-V Split-gate Trench VDMOS and Conventional Trench VDMOS 4

A Comparative study on Total Ionizing Dose Effects of 100-V ...

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4th International Conference on Electrical, Communication and Computer Engineering, ICECCE 2023

作者： Wang, Yuan Zhang, Yuming Zhang, Xun Zhang, Yanlin Xiong, Te Yin, Rongjie Wu, Hao Jiang, Jie Hu, Shengdong School of Microelectronics and Communication Engineering Chongqing University Chongqing China Analog IC Design Center Sichuan Institute of Solid-State Circuits Chongqing China National Key Laboratory of Integrated Circuits and Microsystems School of Microelectronics Chongqing China

ISBN: (纸本)9798350369694

In this paper, we present a comparative study on the effects of Total Ionizing Dose (TID) radiation on the Split-Gate Trench VDMOS (SGT-MOS) and the conventional Trench VDMOS (T-MOS), both with equal rated breakdown voltages of 100 V, using experimental methods. The experimental findings reveal that the same degradation trends in the threshold voltage (Vth) were found for both types of devices. However, the breakdown voltage (BV) of SGT-MOS exhibits greater sensitivity to TID radiation compared to the T-MOS. Utilizing Sentaurus TCAD, we analyze and discuss the variances in BV shifting behavior between the SGT-MOS and T-MOS. The differences in BV shifting behavior between SGT-MOS and T-MOS can be attributed to the positive oxide trapped charges induced by TID, which could significantly affect the electric field distribution for SGT-MOS, but not for T-MOS. To address this issue, three methods are proposed to enhance the TID tolerance for the SGT-MOS and T-MOS. These methods include avoiding high-temperature processes, reducing the thickness of the oxide layer, and decreasing the doping in the drift layer. © 2023 IEEE.

关键词： Threshold voltage

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Dynamic tuning of terahertz atomic lattice vibration via cross-scale mode coupling to nanomechanical resonance in WSe_(2) membranes

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Microsystems & Nanoengineering 2025年第1期11卷 313-320页

作者： Bo Xu Zejuan Zhang Jiaze Qin Jiaqi Wu Luming Wang Jiankai Zhu Chenyin Jiao Wanli Zhang Juan Xia Zenghui Wang Institute of Fundamental and Frontier Sciences University of Electronic Science and Technology of ChinaChengdu 610054China Hubei Key Laboratory of Micro-Nanoelectronic Materials and Devices Hubei UniversityWuhan 430062China State Key Laboratory of Precision Measuring Technology and Instruments(Tianjin University) Tianjin 300350China School of Integrated Sciences and Engineering(Exemplary School of Microelectronics) University of Electronic Science and Technology of ChinaChengdu 610054China State Key Laboratory of Electronic Thin Films and Integrated Devices University of Electronic Science and Technology of ChinaChengdu 610054China

Nanoelectromechanical systems(NEMS)based on atomically-thin tungsten diselenide(WSe_(2)),benefiting from the excellent material properties and the mechanical degree of freedom,offer an ideal platform for studying and exploiting dynamic strain engineering and cross-scale vibration coupling in two-dimensional(2D)***,such opportunity has remained largely unexplored for WSe_(2)NEMS,impeding exploration of exquisite physical processes and realization of novel device ***,we demonstrate dynamic coupling between atomic lattice vibration and nanomechanical resonances in few-layer WSe_(2)*** a custom-built setup capable of simultaneously detecting Raman and motional signals,we accomplish cross-scale mode coupling between the THz crystal phonon and MHz structural vibration,achieving GHz frequency tuning in the atomic lattice modes with a dynamic gauge factor of 61.9,the best among all 2D crystals reported to *** findings show that such 2D NEMS offer great promises for exploring cross-scale physics in atomically-thin semiconductors.

关键词： dynamic strain engineering dynamic tuning nanomechanical resonance cross scale mode coupling nanoelectromechanical systems terahertz atomic lattice vibration exploration exquisite physical processes nanoelectromechanical systems nems based

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Vertical nanowire/nanosheet FETs with a horizontal channel for threshold voltage modulation

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Journal of Semiconductors 2022年第1期43卷 81-89页

作者： Yongbo Liu Huilong Zhu Yongkui Zhang Xiaolei Wang Weixing Huang Chen Li Xuezheng Ai Qi Wang Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of SciencesBeijing 100029China University of Chinese Academy of Sciences Beijing 100049China University of Science and Technology of China Hefei 230026China

A new type of vertical nanowire(VNW)/nanosheet(VNS)FETs combining a horizontal channel(HC)with bulk/back-gate electrode configuration,including Bulk-HC and FD-SOI-HC VNWFET,is proposed and investigated by TCAD *** were carried out between conventional VNWFET and the proposed ***-SOI-HC VNWFET exhibits better Ion/Ioff ratio and DIBL than Bulk-HC *** impact of channel doping and geometric parameters on the electrical character-istic and body factor(γ)of the devices was ***,threshold voltage modulation by bulk/back-gate bias was im-plemented and a largeγis achieved for wide range V_(th)*** addition,results of I_(on)enhancement and Ioff reduction in-dicate the proposed devices are promising candidates for performance and power optimization of NW/NS circuits by adopting dynamic threshold voltage *** results of preliminary experimental data are discussed as well.

关键词： vertical nanowire nanosheet silicon on insulator(SOI) threshold voltage multi-V_(th) threshold voltage modulation

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A 67F2 Reconfigurable PUF Using 1T2R RRAM Switching Competition in 28nm CMOS with 5e-9 Bit Error Rate

A 67F2 Reconfigurable PUF Using 1T2R RRAM Switching Competit...

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2024 IEEE Symposium on VLSI Technology and circuits, VLSI Technology and circuits 2024

作者： Cao, Yue Yang, Honghu Yang, Jianguo Liu, Qi Liu, Ming Frontier Institute of Chip and System Fudan University Shanghai China Zhangjiang Laboratory Shanghai China State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing China

ISBN: (纸本)9798350361469

Aiming at low-cost, high-reliability hardware security in IoT applications, we demonstrated a 1Mb 1T2R RRAM Reconfigurable PUF design. A 1T2R PUF cell with a smaller size utilizes the switch time variation in the RRAM device as the entropy source, and an initialization-extraction process that exploits the cycle-to-cycle switch time variation is proposed to enable PUF reconfiguration. A self-adaptive extraction circuit and a reprogram calibration scheme are designed to improve operation power and native BER. Moreover, a symmetrical read scheme is employed to enhance power analysis resilience, by balancing the power during PUF readout. The test chip achieves a cell size of 67F2 and a native (calibrated) BER of 0.021% ( © 2024 IEEE.

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Vertical SnS2/Si heterostructure for tunnel diodes

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Science China(Information Sciences) 2020年第2期63卷 189-195页

作者： Rundong JIA Qianqian HUANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University

Tunneling FET（TFET） is considered as one of the most promising low-power electronic devices,however, suffers from the low drive current. Heterostructure TFET with low effective tunnel barrier height based on traditional 3D materials can obtain large tunnel current but deteriorated off-state current induced by the lattice mismatch. van der Waals heterostructure TFET based on 2D materials can obtain danglingbond-free interface for suppressed off-state current but face the challenge of controllable and stable doping technology. As the critical building block of the TFET, tunnel diode based on the 2D/3D heterostructure is proposed in this study and experimentally demonstrated. Combination of the pristine interface of 2D materials and matured doping technology in the traditional 3D bulk materials, tunnel diodes based on the 2D/3D heterostructures are expected to realize low leakage current and high on current simultaneously,showing great potential in low-power electronics. The N+SnS2/P+Si heterostructure with effective tunnel barrier of 0.17 eV theoretically is considered for the first time and selected as the optimal material platform for tunnel diodes. The N+SnS2/P+Si tunnel diode demonstrated experimentally shows the high current density of 1 μA/μm2, which is the highest one among the reported tunnel diodes based on the 2D/group IV materials. The tunneling current is also confirmed by low-temperature measurements. This study shows the great potential of the 2D/3D heterostructure for low-power tunneling devices.

关键词： 2D/3D heterostructure SnS2/Si tunnel barrier tunnel diode energy-efficient

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Design and validation of RLC equivalent circuit model based on long-wave infrared metamaterial absorber

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红外与毫米波学报 2025年第1期44卷 129-137页

作者： ZHAO Ji-Cong DANG Yan-Meng HOU Hai-Yang LIN Ye-Fan SUN Hai-Yan ZHANG Kun School of Microelectronics and School of Integrated Circuits Nantong UniversityNantong 226019China State Key Laboratory of Infrared Physics Shanghai Institute of Technical PhysicsChinese Academy of SciencesShanghai 200083China

In this paper,we propose an RLC equivalent circuit model theory which can accurately predict the spectral response and resonance characteristics of metamaterial absorption structures,extend its design,and characterize the parameters of the model in *** employing this model,we conducted computations to characterize the response wavelength and bandwidth of variously sized metamaterial absorbers.A comparative analysis with Finite Difference Time Domain(FDTD)simulations demonstrated a remarkable level of consistency in the *** designed absorbers were fabricated using micro-nano fabrication processes,and were experimentally tested to demonstrate absorption rates exceeding 90%at a wavelength of 9.28μ*** predicted results are then compared with test *** comparison reveals good consistency in two aspects of the resonance responses,thereby confirming the rationality and accuracy of this model.

关键词： metamaterial surface plasmons magnetic dipoles RLC circuit model

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First large-scale (68×25×5 nm3) atomistic modeling for accurate and efficient etching process based on machine learning molecular dynamics (MLMD)

First large-scale (68×25×5 nm3) atomistic modeling for acc...

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2024 IEEE International Electron devices Meeting, IEDM 2024

作者： Feng, Zemeng Hu, Ziyi Yu, Tong Lai, Panpan Ge, Rui Shao, Hua Shang, Dashan Li, Zhiqiang Xu, Kui Li, Junjie Chen, Rui Li, Ling State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China

ISBN: (纸本)9798350365429

Revealing the reaction mechanisms in manufacturing advanced devices is crucial for enhancing performance at nodes below 3 nm. In this study, we introduce the first large-scale atomistic model utilizing a machine learning molecular dynamics (MLMD) framework. This model simulates the lateral isotropic selective etching process of SiO2/Si stack structures in Gate-all-around field-effect transistors (GAAFETs) using F* radical plasma. The dataset for this model is generated using active learning strategies based on search for F* radical reacting with Si(100) substrate. Our simulation spans 68×25×5 nm3, involving over 600,000 atoms, and demonstrates a 4× improvement in model error for etching reaction trends compared to the classic molecular dynamics (CMD) method. Additionally, the model achieves a typical runtime of 16.7 hours, representing a ~44.9× speedup over CMD. Moreover, the simulation provides detailed reaction path and uncovers the mechanisms behind lateral etching. This framework paves the way for potential atom-to-device multiscale process modeling, contributing to Design Technology Co-optimization (DTCO). © 2024 IEEE.

关键词： Gallium arsenide

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Simultaneous microwave characterization of wafer-level optoelectronic transceiver chips based on photonic sampling and mapping

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Science China(Information Sciences) 2024年第2期67卷 337-338页

作者： Yutong HE Xinhai ZOU Ying XU Zhihui LI Naidi CUI Junbo FENG Yali ZHANG Zhiyao ZHANG Shangjian ZHANG Yong LIU Ninghua ZHU Research Center for Microwave Photonics State Key Laboratory of Electronic Thin Films and Integrated DevicesSchool of Optoelectronic Science and EngineeringUniversity of Electronic Science and Technology of China Chongqing United Microelectronics Center (CUMEC) Xiongan Institute of Innovation Chinese Academy of Sciences

Photonic integrated circuits(PICs) promise future parallelism growths of high-performance communication, computation, and offer unprecedented bandwidth scalability with reduced power consumption as a viable replacement for an electrical wire with an optoelectronic transceiver consisting of a transmitter and a receiver integrated on the same wafer.

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