The comprehensive understanding of the structure-dependent electrostatic discharge behaviors in a conventional diode-triggered silicon controlled rectifier (DTSCR) is presented in this paper. Combined with the devic...
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The comprehensive understanding of the structure-dependent electrostatic discharge behaviors in a conventional diode-triggered silicon controlled rectifier (DTSCR) is presented in this paper. Combined with the device simulation, a mathematical model is built to get a more in-depth insight into this phenomenon. The theoretical studies are verified by the transmission-line-pulsing (TLP) test results of the modified DTSCR structure, which is realized in a 65-nm complementary metal-oxide-semiconductor (CMOS) process. The detailed analysis of the physical mechanism is used to provide predictions as the DTSCR-based protection scheme is required. In addition, a method is also presented to achieve the tradeoff between the leakage and trigger voltage in DTSCR.
Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. ...
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Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InCaP barrier layer. The direct-current Id-Vg measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △Vg in the oncurrent region. The Id-Vg degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced aeceptor traps contain both permanent and recoverable traps. Compared with surface channel InCaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.
Nanoionics based devices and networks are intriguing candidates for the construction of new computing systems that could perform intelligent and energy-efficient *** this talk,I will discuss recent progresses in the d...
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Nanoionics based devices and networks are intriguing candidates for the construction of new computing systems that could perform intelligent and energy-efficient *** this talk,I will discuss recent progresses in the development of neuromorphic devices and networks,as well as a few critical challenges existing in the mechanism,device and network levels that must be overcome[1-2].
This work presents the design of a novel static-triggered power-rail electrostatic discharge(ESD)clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is fir...
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This work presents the design of a novel static-triggered power-rail electrostatic discharge(ESD)clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is firstly discussed. Based on the discussion, a novel power-rail ESD clamp circuit utilizing the static ESD detection mechanism is proposed. By skillfully incorporating a thyristor delay stage into the trigger circuit(TC), the proposed circuit achieves the best ESD-conduction behavior while consuming the lowest leakage current(Ileak) at the normal bias voltage among all investigated circuits in this work. In addition, the proposed circuit achieves an excellent false-triggering immunity against fast power-up pulses. All investigated circuits are fabricated in a 65-nm CMOS process. Performance superiorities of the proposed circuit are fully verified by both simulation and test results. Moreover, the proposed circuit offers an efficient on-chip ESD protection scheme considering the worst discharge case in the utilized process.
This paper presents a novel design of a ternary SRAM sense amplifier using carbon nanotube field-effect transistors(CNFETs).Chirality of CNFET is used to control the threshold voltage to realize the ternary *** result...
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This paper presents a novel design of a ternary SRAM sense amplifier using carbon nanotube field-effect transistors(CNFETs).Chirality of CNFET is used to control the threshold voltage to realize the ternary *** results using HSPICE shows that the proposed SRAM sense amplifier perform correctly at 0.9 V supply voltage in the ternary SRAM read *** it can achieve 87.5% and 88.5% enhancement in speed,84.2% and 85.6% in PDP,compared with a ternary DRAM sense amplifier and the ternary SRAM without sense amplifier.
In the above paper, there is an error in the information of corresponding author’s email address. The corrected corresponding author’s email address information is provided.
In the above paper, there is an error in the information of corresponding author’s email address. The corrected corresponding author’s email address information is provided.
Dear editor,The Silicon controlled rectifiers(SCR)are widely used to protect integrated circuits(ICs)from electrostatic discharge(ESD)and electrical overstress(EOS)damage[1].An accurate SCR model is highly desirable i...
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Dear editor,The Silicon controlled rectifiers(SCR)are widely used to protect integrated circuits(ICs)from electrostatic discharge(ESD)and electrical overstress(EOS)damage[1].An accurate SCR model is highly desirable in on-chip ESD protection *** studies modeled SCRs by aggregating conventional bipolar junction transistor(BJT)models and adding extra physical models that conventional BJT models fail to support[2,3].However the auxiliary models are mostly complicated
This paper presents a novel integrated Schottky barrier diode temperature sensor in a 4H-SiC power MOSFET. Dual electrical isolation and additional current path are applied to this temperature sensor, allowing the sen...
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This paper presents a novel integrated Schottky barrier diode temperature sensor in a 4H-SiC power MOSFET. Dual electrical isolation and additional current path are applied to this temperature sensor, allowing the sensor to work properly in any operating state of power MOSFET. Due to the sufficient electrical isolation, the crosstalk between sensor and power MOSFET is almost eliminated. Furthermore, high sensitivity S=1.21mV/K is observed for a constant bias current of I d =1mA. The temperature sensor exhibits a good degree of linearity with a root mean square error R 2 =0.99996.
The 4H-SiC ultraviolet detector of the MESFET structure with gain is proposed and simulated in this paper. The Schottky gate of MESFET is transparent or semi-transparent to allow more of the incident UV light to be ab...
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