The 4H-SiC n-p-n BJT for ultraviolet detection with high optical gain is proposed and optimized in this paper. The effect of structural parameters of 4H-SiC phototransistor on the performance of the detectors is simul...
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The n-p-i-n AlGaN solar-blind ultraviolet double heterojunction phototransistor (DHPT) with internal gain is proposed and optimized in this paper. The dependences of spectral responsivity and quantum gain on structure...
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In this paper, Ge surface passivation by Ge O2 grown by N2 O plasma oxidation is presented and experimentally demonstrated. Results show that stoichiometrically Ge O2 can be achieved by N2 O plasma oxidation at 350...
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In this paper, Ge surface passivation by Ge O2 grown by N2 O plasma oxidation is presented and experimentally demonstrated. Results show that stoichiometrically Ge O2 can be achieved by N2 O plasma oxidation at 350°C. The transmission electron microscope observation reveals that the Ge O2/Ge interface is automatically smooth and the thickness of Ge O2is～0.9 nm with 120 s N2 O plasma oxidation. The interface state density of Ge surface after N2 O plasma passivation is about～3×1011 cm-2e V-1. With Ge O2 passivation,the hysteresis of MOS capacitor with Al2O3 as gate dielectric is reduced to～55 m V, compared to 130 m V of the untreated one. The Fermi-level at Ge O2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage, which is promising for high performance NMOSFETs fabrication.
In this paper, the challenge of gate-all-around nanowire transistor for low power application is uncovered and discussed from experimental and TCAD simulation. For promising low power application, gate-all-around nano...
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In this paper, the challenge of gate-all-around nanowire transistor for low power application is uncovered and discussed from experimental and TCAD simulation. For promising low power application, gate-all-around nanowire transistor faces more difficulties than expected due to abnormal gate-induced-drain-leakage current behavior. The study shows that as nanowire diameter shrinks, GIDL current will become worse rather than suppressed. The gate coupling modulated drain-to-body electric field is found responsible for the increased GIDL current in the extremely scaled nanowire. To overcome the challenge of GAA SNWT in low power application, a practical design is proposed by optimization of overlap length and drain junction gradient considering the trade-off between short channel effect and performance.
The effects of the physical damages induced by heavy ion irradiation on the performance of partiallydepleted SOI devices are experimentally investigated. After heavy ion exposure, different degradation phenomena are o...
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The effects of the physical damages induced by heavy ion irradiation on the performance of partiallydepleted SOI devices are experimentally investigated. After heavy ion exposure, different degradation phenomena are observed due to the random strike of heavy ions. A decrease of the saturation current and transconductance,and an enhanced gate-induced drain leakage current are observed, which are mainly attributed to the displacement damages that may be located in the channel, the depletion region of the drain/body junction or the gate-to-drain overlap region. Further, PDSOI devices with and without body contact are compared, which reveals the differences in the threshold voltage shift, the drain-induced barrier lowing effect, the transconductance and the kink effect. The results may provide a guideline for radiation hardened design.
The impact of process induced variation on the response of SOI Fin FET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When Fin FET biased at OFF state configuration（Vgs D0, Vds DV...
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The impact of process induced variation on the response of SOI Fin FET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When Fin FET biased at OFF state configuration（Vgs D0, Vds DVdd/ is struck by a heavy ion, the drain collects ionizing charges under the electric field and a current pulse（single event transient, SET） is consequently formed. The results reveal that with the presence of line-edge roughness（LER）, which is one of the major variation sources in nano-scale Fin FETs, the device-to-device variation in terms of SET is observed. In this study, three types of LER are considered： type A has symmetric fin edges, type B has irrelevant fin edges and type C has parallel fin edges. The results show that type A devices have the largest SET variation while type C devices have the smallest variation. Further, the impact of the two main LER parameters,correlation length and root mean square amplitude, on SET variation is discussed as well. The results indicate that variation may be a concern in radiation effects with the down scaling of feature size.
In this paper, the improved recrystallization of ultra-thin amorphous silicon (α-Si) film was realized by two-dimensionally confined lattice regrowth with normal rapid thermal annealing process. By experimental inves...
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In this paper, the improved recrystallization of ultra-thin amorphous silicon (α-Si) film was realized by two-dimensionally confined lattice regrowth with normal rapid thermal annealing process. By experimental investigation, the α-Si films with thickness of 400 Å were found to be recrystallized even at 850°C for only 35s rapid thermal annealing (RTA). With capped Si 3 N 4 layer, the lattice regrowth was confined more strictly to along the film plane so that smoother and higher-quality polycrystalline silicon film was obtained which is suitable for future monolithic three dimensional (3D) stacked integration processes.
Transient behaviors of the diode-triggered silicon controlled rectifiers (DTSCRs) under very-fast transmission line pulse (VF-TLP) testing are investigated in this paper. The underlying physics needs to be comprehensi...
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Transient behaviors of the diode-triggered silicon controlled rectifiers (DTSCRs) under very-fast transmission line pulse (VF-TLP) testing are investigated in this paper. The underlying physics needs to be comprehensively investigated and 2D/3D device simulations are well performed and compared. Analysis uncovers that the turn-on process of intrinsic SCR is ascribed to Darlington effect as well as junction breakdown.
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