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13th Asia-Pacific International Symposium on Electromagnetic Compatibility and Technical Exhibition, APEMC 2022

作者： Xu, Ji Wang, Da-Wei Liu, Jun Su, Guo-Dong Zhao, Wen-Sheng Xi'An Jiaotong University Key Lab of Micro-Nano Electronics and System Integration of xi'An City School of Microelectronics Shaanxi Xi'an710049 China Hangzhou Dianzi University Zhejiang Prov. Key Lab of Large-Scale Integrated Circuit Design School of Electronics Information Zhejiang Hangzhou310018 China

ISBN: (数字)9781665416719

ISBN: (纸本)9781665416719

Based on the wafer level packaging technology, different widths and lengths of the strip line was designed, fabricate and measured. Meanwhile, to characterize the high frequency characteristics of the strip line, the skin effect has been considered to the transmission line theory equivalent circuit model. The proposed model is in good agreement with the measured data of the strip line in the frequency range of 10 GHz - 110 GHz. The proposed model can effectively support the co-simulation of the active device model and passive device model in heterogeneous integrated package, accelerate the optimization speed of circuit design iteration, and help reduce the time cost of the EM simulation of layout. © 2022 IEEE.

关键词： Equivalent circuits

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An Adaptive Bionic Sensor: Enhancing Ankle Joint Tracking with High Sensitivity and Superior Cushioning Performance

SSRN

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SSRN 2024年

作者： Jin, Jianqiao Zhang, Chen Zhao, Jianyuan Yu, Minghan Lei, Ming Jin, Chun Yin, Rui Zhao, Weiwei Sauvage Laboratory for Smart Materials The School of Integrated Circuit Harbin Institute of Technology Shenzhen518055 China Shenzhen Key Laboratory of Flexible Printed Electronics Technology Harbin Institute of Technology Shenzhen518055 China State Key Laboratory of Advanced Welding & Joining Harbin Institute of Technology Harbin150001 China Human-Computer Interaction Design Lab School of System Design and Intelligent Manufacturing Southern University of Science and Technology Shenzhen518055 China

Flexible sensors are renowned for their rapid responsiveness, high flexibility, and outstanding mechanical properties, making them ideal for applications in wearable devices, sports and health monitoring, and human-machine interfaces. To enhance the sensing performance of these flexible sensors, researchers have drawn inspiration from nature, creating various bionic microstructures. However, these structures often manifest in the macroscopic form of thin films, which do little to improve impact resistance and joint protection. In response, this work achieves a highly sensitive and impact-resistant pressure sensor by integrating bionic principles at both micro and macro levels. Specifically, at the micro level, a muscle-like hydrogel system consisting of MXene nanosheets incorporated into the double network of polyvinyl alcohol and sodium alginate matrix is selected. At the macro level, the bionic prototypes of mimosa leaves and durian spikes with good energy absorption structure, together with octopus’ sucker with good adsorption capacity are selected, and the synergistic construction of the three structures is realized through 3D printing methods. The obtained sensor has an appropriate response range, sensitivity and stability. More importantly, the displacement deformation of the hydrogel can be reduced by 91.22%, while its adhesion strength can be increased by 57.5% compared to the unstructured hydrogel. As a proof-of-concept, the proposed bionic flexible sensor can be used to monitor the motion status of the human ankle joint in real-time, thereby assisting users in making real-time judgments on gait health. © 2024, The Authors. All rights reserved.

关键词： Sodium alginate

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An Efficient Multi-fidelity Bayesian Optimization Approach for Analog circuit Synthesis

arXiv

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arXiv 2019年

作者： Zhang, Shuhan Lyu, Wenlong Yang, Fan Yan, Changhao Zhou, Dian Zeng, Xuan Hu, Xiangdong State Key Lab of ASIC & System Microelectronics Department Fudan University China Shanghai High Performance Integrated Circuit Design Center China University of Texas at Dallas Dallas United States

This paper presents an efficient multi-fidelity Bayesian optimization approach for analog circuit synthesis. The proposed method can significantly reduce the overall computational cost by fusing the simple but potentially inaccurate low-fidelity model and a few accurate but expensive high-fidelity data. Gaussian Process (GP) models are employed to model the low- and high-fidelity black-box functions separately. The nonlinear map between the low-fidelity model and high-fidelity model is also modelled as a Gaussian process. A fusing GP model which combines the low- and high-fidelity models can thus be built. An acquisition function based on the fusing GP model is used to balance the exploitation and exploration. The fusing GP model is evolved gradually as new data points are selected sequentially by maximizing the acquisition function. Experimental results show that our proposed method reduces up to 65.5% of the simulation time compared with the state-of-the-art single-fidelity Bayesian optimization method, while exhibiting more stable performance and a more promising practical prospect. Copyright © 2019, The Authors. All rights reserved.

关键词： Timing circuits

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design of Sequential Elements for Low Power Clocking system

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2011年第5期19卷 914-918页

作者： Zhao, Peiyi McNeely, Jason Kuang, Weidong Wang, Nan Wang, Zhongfeng Chapman Univ Schmid Coll Sci Sch Computat Sci Integrated Circuit Design & Embedded Syst Lab Orange CA 92604 USA Univ Louisiana Lafayette Ctr Adv Comp Studies Lafayette LA 70504 USA Univ Texas Pan Amer Dept Elect Engn Edinburg TX 78539 USA Broadcom Corp Irvine CA 92602 USA

Power consumption is a major bottleneck of system performance and is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flop-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them is an effective way to reduce capacity of the clock load by minimizing number of clocked transistors. To approach this, we propose a novel clocked pair shared flip-flop which reduces the number of local clocked transistors by approximately 40%. A 24% reduction of clock driving power is achieved. In addition, low swing and double edge clocking, can be easily incorporated into the new flip-flop to build clocking systems.

关键词： Flip-flop low power

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Power optimization for VLSI circuits and systems

Power optimization for VLSI circuits and systems

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2010 10th IEEE International Conference on Solid-State and integrated circuit Technology

作者： Zhao, Peiyi Wang, Zhongfeng Hang, Guoqiang Integrated Circuit Design and Embedded System Lab. School of Computational Science Chapman University Orange CA 92604 United States Information and Electronic Engineering Department Zhejiang University Hangzhou China Broadcom Corp. Irvine CA United States

ISBN: (纸本)9781424457984

Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level. This paper gives a brief overview of low power design principals, then focuses discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems. Finally we discuss low power optimization techniques at system and architecture level. ©2010 IEEE.

关键词： VLSI circuits

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Power Optimization for VLSI circuits and systems

Power Optimization for VLSI Circuits and Systems

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2010 10th IEEE International Conference on Solid-State and integrated circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Peiyi Zhao Zhongfeng Wang Guoqiang Hang Integrated Circuit Design and Embedded System Lab School of Computational Science Chapman University Orange CA USA Broadcom Corporation Irvine CA USA Information and Electronic Engineering Department University of Zhejiang Hangzhou China

关键词： low power VLSI clocking system flip-flop

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Low power design of VLSI circuits and systems

Low power design of VLSI circuits and systems

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2009 8th IEEE International Conference on ASIC, ASICON 2009

作者： Zhao, Peiyi Wang, Zhongfeng Integrated Circuit Design and Embedded System Lab. Math and Computer Science Department Chapman University Orange CA 92604 United States Broadcom Corp. Irvine CA United States

ISBN: (纸本)9781424438686

Power consumption is the bottleneck of system performance and is listed as one of the top three challenges in ITRS 2008. Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level. This paper first gives a brief overview for low power optimization techniques at system and architecture level, then focus discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems. ©2009 IEEE.

关键词： Flip flop circuits

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Low power design of vlsi circuits and systems

Low power design of vlsi circuits and systems

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International Conference on ASIC

作者： Peiyi Zhao Zhongfeng Wang Integrated Circuit Design and Embedded System Lab Math and Computer Science Department Chapman University Orange CA USA Broadcom Corporation Irvine CA USA

关键词： Very large scale integration circuits and systems Clocks Energy consumption design optimization Frequency Power dissipation system performance Flip-flops Latches

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Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply systems

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2009年第9期17卷 1196-1202页

作者： Zhao, Peiyi McNeely, Jason B. Golconda, Pradeep K. Venigalla, Soujanya Wang, Nan Bayoumi, Magdy A. Kuang, Weidong Downey, Luke Chapman Univ Dept Math & Comp Sci Integrated Circuit Design & Embedded Syst Lab Orange CA 92604 USA Univ Louisiana Lafayette Ctr Adv Comp Studies Lafayette LA 70504 USA W Virginia Univ Dept Elect & Comp Engn Inst Technol Montgomery WV 25136 USA Intel Corp Folsom CA 95630 USA Univ Texas Pan Amer Dept Elect Engn Edinburg TX 78539 USA

Clustered voltage scaling (CVS) is an effective way to decrease power dissipation. One of the design challenges is the design of an efficient level converter with fewer power and delay overheads. In this paper, level-shifting flip-flop topologies are investigated. Different level-shifting schemes are analyzed and classified into groups: differential style, n-type metal-oxide-semiconductor (NMOS) pass-transistor style, and precharged style. An efficient level-shifting scheme, the clocked-pseudo-NMOS (CPN) level conversion scheme, is presented. One novel level conversion flip-flop (CPN-LCFF) is proposed, which combines the conditional discharge technique and pseudo-NMOS technique. In view of power and delay, the new CPN-LCFF outperforms previous LCFF by over 8% and 15.6%, respectively.

关键词： Dual supply flip-flop level conversion low power

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Low-power clock branch sharing double-edge triggered flip-flop

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2007年第3期15卷 338-345页

作者： Zhao, Peiyi McNeely, Jason Golconda, Pradeep Bayoumi, Magdy A. Barcenas, Robert A. Kuang, Weidong Chapman Univ Integrated Circuit Design & Embedded Syst Lab Dept Math & Comp Sci Orange CA 92604 USA Univ Louisiana Ctr Adv Comp Studies Lafayette LA 70504 USA Intel Corp Folsom CA 95630 USA Pan Amer Univ Dept Elect Engn Edinburg TX 78539 USA

In this paper, a new technique for implementing low-energy double-edge triggered flip-flops is introduced. The new technique employs a clock branch-sharing scheme to reduce the number of clocked transistors in the design. The newly proposed design also employs conditional discharge and split-path techniques to further reduce switching activity and short-circuit currents, respectively. As compared to the other state of the art double-edge triggered flip-flop designs, the newly proposed CBS_ip design has an improvement of up to 20% and 12.4% in view of power consumption and PDP, respectively.

关键词： CMOS double edge flip-flop low power

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