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Selected Crosstalk Avoidance Code for Reliable Network-on-Chip

Journal of computer Science & technology 2009年第6期24卷 1074-1085页

作者：张颖李华伟李晓维 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Graduate School of the Chinese Academy of Sciences

With the shrink of the technology into nanometer scale, network-on-chip （NOC） has become a reasonable solution for connecting plenty of IP blocks on a single chip. But it suffers from both crosstalk effects and single event upset （SEU）, especially crosstalk-induced delay, which may constrain the overall performance of NOC. In this paper, we introduce a reliable NOC design using a code with the capability of both crosstalk avoidance and single error correction. Such a code, named selected crosstalk avoidance code （SCAC） in our previous work, joins crosstalk avoidance code （CAC） and error correction code （ECC） together through codeword selection from an original CAC codeword set. It can handle possible error caused by either crosstalk effects or SEU. When designing a reliable NOC, data are encoded to SCAC codewords and can be transmitted rapidly and reliably across NOC. Experimental results show that the NOC design with SCAC achieves higher performance and is reliable to tolerate single errors. Compared with previous crosstalk avoidance methods, SCAC reduces wire overhead, power dissipation and the total delay. When SCAC is used in NOC, it can save 20% area overhead and reduce 49% power dissipation.

关键词： crosstalk avoidance codeword selection reliable network-on-chip single event upset

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Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment

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Journal of computer Science & technology 2007年第5期22卷 673-680页

作者：王伟胡瑜韩银和李晓维张佑生 School of Computer and Information Hefei University of Technology Hefei 230009China Key Laboratory of Computer System and ArchitectureInstitute of Computing TechnologyChinese Academy of Sciences Beijing 100080China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080China School of Computer and Information Hefei University of Technology Hefei 230009China

It is a well-known fact that test power consumption may exceed that during functional operation. Leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor （CMOS） circuits during test has become a significant part of the total power dissipation. Hence, it is important to reduce leakage power to prolong battery life in portable systems which employ periodic self-test, to increase test reliability and to reduce test cost. This paper analyzes leakage current and presents a kind of leakage current simulator based on the transistor stacking effect. Using it, we propose techniques based on don＇t care bits （denoted by Xs） in test vectors to optimize leakage current in integrated circuit （IC） test by genetic algorithm. The techniques identify a set of don＇t care inputs in given test vectors and reassign specified logic values to the X inputs by the genetic algorithm to get minimum leakage vector （MLV）. Experimental results indicate that the techniques can effectually optimize leakage current of combinational circuits and sequential circuits during test while maintaining high fault coverage,

关键词： leakage current don＇t care bits minimum leakage vector leakage power

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Online Distributed Fault Detection of Sensor Measurements

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Tsinghua Science and technology 2007年第S1期12卷 192-196页

作者：高建良徐勇军李晓维 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

In wireless sensor networks (WSNs), a faulty sensor may produce incorrect data and transmit them to the other sensors. This would consume the limited energy and bandwidth of WSNs. Furthermore, the base station may make inappropriate decisions when it receives the incorrect data sent by the faulty sensors. To solve these problems, this paper develops an online distributed algorithm to detect such faults by exploring the weighted majority vote scheme. Considering the spatial correlations in WSNs, a faulty sensor can diagnose itself through utilizing the spatial and time information provided by its neighbor sensors. Simulation results show that even when as many as 30% of the sensors are faulty, over 95% of faults can be correctly detected with our algorithm. These results indicate that the proposed algorithm has excellent performance in detecting fault of sensor measurements in WSNs.

关键词： wireless sensor networks fault diagnosis fault detection fault tolerance spatial correlation

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High Performance General-Purpose Microprocessors： Past and Future

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Journal of computer Science & technology 2006年第5期21卷 631-640页

作者：胡伟武侯锐肖俊华章隆宾 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 P.R. China

It can be observed from looking backward that processor architecture is improved through spirally shifting from simple to complex and from complex to simple. Nowadays we are facing another shifting from complex to simple, and new innovative architecture will emerge to utilize the continuously increasing transistor budgets. The growing importance of wire delays, changing workloads, power consumption, and design/verification complexity will drive the forthcoming era of Chip Multiprocessors （CMPs）. Furthermore, typical CMP projects both from industries and from academics are investigated. Through going into depths for some primary theoretical and implementation problems of CMPs, the great challenges and opportunities to future CMPs are presented and discussed. Finally, the Godson series microprocessors designed in China are introduced.

关键词： high performance general-purpose microprocessor instruction level parallelism data level parallelism thread level parallelism chip multiprocessors Godson processor

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Design for Testability Features of Godson-3 Multicore Microprocessor

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Journal of computer Science & technology 2011年第2期26卷 302-313页

作者：齐子初刘慧李向库胡伟武 Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Chinese Academy of Sciences Loongson Technologies Corporation Limited

This paper describes the design for testability （DFT） challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar （SMOC） on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism （TAM） is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.

关键词： DFT （design for testability） TAM （test access mechanism） multicore processor low power test

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Physical Implementation of the 1GHz Godson-3 Quad-Core Microprocessor

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Journal of computer Science & technology 2010年第2期25卷 192-199页

作者：范宝峡杨梁王江嵋王茹肖斌徐英刘动赵继业 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences Loongson Technology Corporation Limited

The Godson-3A microprocessor is a quad-core version of the scalable Godson-3 multi-core series. It is physically implemented based on the 65 nm CMOS process. This 174 mm2 chip consists of 425 million transistors. The maximum frequency is 1GHz with a maximum power consumption of 15 W. The main challenges of Godson-3A physical implementation include very large scale, high frequency requirement, sub-micron technology effects and aggressive time schedule. This paper describes the design methodology of the physical implementation of Godson-3A, with particular emphasis on design methods for high frequency, clock tree design, power management, and on-chip variation （OCV） issue.

关键词： physical implementation design methodology on-chip variation （OCV） low power clock tree

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Dawning Nebulae:A PetaFLOPS Supercomputer with a Heterogeneous Structure

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Journal of computer Science & technology 2011年第3期26卷 352-362页

作者：孙凝辉邢晶霍志刚谭光明熊劲李波马灿 Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Chinese Academy of Sciences Graduate University of Chinese Academy of Sciences

Dawning Nebulae is a heterogeneous system composed of 9280 multi-core x86 CPUs and 4640 NVIDIA Fermi GPUs. With a Linpack performance of 1.271 petaFLOPS, it was ranked the second in the TOP500 List released in June 2010. In this paper, key issues in the system design of Dawning Nebulae are introduced. system tuning methodologies aiming at petaFLOPS Linpack result are presented, including algorithmic optimization and communication improvement. The design of its file I/O subsystem, including HVFS and the underlying DCFS3, is also described. Performance evaluations show that the Linpack efficiency of each node reaches 69.89%, and 1024-node aggregate read and write bandwidths exceed 100 GB/s and 70 GB/s respectively. The success of Dawning Nebulae has demonstrated the viability of CPU/GPU heterogeneous structure for future designs of supercomputers.

关键词： supercomputer heterogeneous systems performance evaluation

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Helix Scan:A Scan Design for Diagnosis

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Tsinghua Science and technology 2007年第S1期12卷 83-88页

作者：王飞胡瑜李晓维 Graduate School of Chinese Academy of Sciences Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

Scan design is a widely used design-for-testability technique to improve test quality and efficiency. For the scan-designed circuit, test and diagnosis of the scan chain and the circuit is an important process for silicon debug and yield learning. However, conventional scan designs and diagnosis methods abort the subsequent diagnosis process after diagnosing the scan chain if the scan chain is faulty. In this work, we propose a design-for-diagnosis scan strategy called helix scan and a diagnosis algorithm to address this issue. Unlike previous proposed methods, helix scan has the capability to carry on the diagnosis process without losing information when the scan chain is faulty. What is more, it simplifies scan chain diagnosis and achieves high diagnostic resolution as well as accuracy. Experimental results demonstrate the effectiveness of our design.

关键词： test diagnosis scan chain diagnosis design for diagnosis (DFD)

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Reliable and Energy Efficient Protocol for Wireless Sensor Network

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Tsinghua Science and technology 2007年第S1期12卷 95-100页

作者：阚保强蔡理徐勇军 College of Science Air Force Engineering University Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

Low-power design is one of the most important issues in wireless sensor networks (WSNs) , while reliable information transmitting should be ensured as well. Transmitting power (TP) control is a simple method to make the power consumption down, but excessive interferences from potential adjacent operating links and communication reliability between nodes should be considered. In this paper, a reliable and energy efficient protocol is presented, which adopts adaptive rate control based on an optimal TP. A mathematical model considering average interference and network connectivity was used to predict the optimal TP. Then for the optimal TP, active nodes adaptively chose the data rate with the change of bit-error–rate(BER) performance. The efficiency of the new strategy was validated by mathematical analysis and simulations. Compared with 802.11 DCF which uses maximum unified TP and BASIC protocol, it is shown that the higher average throughput can achieve while the energy consumption per useful bit can be reduced according to the results.

关键词： wireless sensor networks reliable communication energy efficient optimal transmitting power adaptive link control

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Fault Tolerance Mechanism in Chip Many-Core Processors

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Tsinghua Science and technology 2007年第S1期12卷 169-174页

作者：张磊韩银和李华伟李晓维 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences Beijing 100080China

As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performance. Effective fault tolerance techniques are essential to improve the yield of such complex chips. In this paper, a core-level redundancy scheme called N+M is proposed to improve N-core processors’ yield by providing M spare cores. In such architecture, topology is an important factor because it greatly affects the processors’ performance. The concept of logical topology and a topology reconfiguration problem are introduced, which is able to transparently provide target topology with lowest performance degradation as the presence of faulty cores on-chip. A row rippling and column stealing (RRCS) algorithm is also proposed. Results show that PRCS can give solutions with average 13.8% degradation with negligible computing time.

关键词： chip many-core processors yield fault tolerance reconfiguration network-on-chip

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