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integrated Organic Electrochemical Transistors for Serotonin Detection and Synaptic Plasticity

IEEE Journal of the Electron Devices Society 2025年

作者： Xie, Yifan Jin, Qingqing Cheng, Miao Tian, Yue Wang, Jinyao Chu, Jingyun Liu, Changrui Li, Mengmeng Chinese Academy of Sciences State Key Laboratory of Fabrication Technologies for Integrated Circuits Beijing100029 China Chinese Academy of Sciences Institute of Microelectronics Beijing100029 China University of Chinese Academy of Sciences School of Integrated Circuits Beijing100049 China

Organic electrochemical transistors (OECTs) have gained increasing attention for their potential in neuromorphic electronics and neurotransmitter sensing, thanks to their inherent low-power operation and high sensitivity. This study introduces an integrated on-chip Ag/AgCl gate architecture for OECTs, which not only exhibits identical performance with devices using traditional external gates but also enables the integration of a uniform 3W3 transistor array. The resulting array demonstrates consistent performance across individual devices, characterized by uniform transconductance, on/off ratios, threshold voltages, and charge-carrier mobility. Notably, these OECTs function as highly sensitive biosensors for serotonin detection, achieving a detection limit of 0.5 nM. Furthermore, exposure to serotonin triggers a transition from short-term to long-term plasticity in the OECTs, mirroring the processes underlying synaptic memory formation. These findings open new avenues for the development of large-area bioelectronics and neuromorphic computing systems. © 2013 IEEE.

关键词： Integration

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Technique of mask optimization for achieving the maximal effective litho-CPW

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Optics Express 2025年第12期33卷 25783-25797页

作者： Jiashuo Wang Hao Shen Xiaojing Su Wei Zhao Lisong Dong Yajuan Su Yayi Wei State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China University of Chinese Academy of Sciences Beijing 100049 China suxiaojing@*** weiyayi@***

Achieving a large lithography process window (PW) via computational lithography is a crucial prerequisite for ensuring adequate product yield in advanced-node integrated-circuit manufacturing technologies. However, as the critical dimensions of patterns continue to shrink, a chip-level qualified common process window (CPW) necessitates multiple rounds of highly time-consuming iterations of source mask co-optimization (SMO). To ensure a sufficient CPW for yield improvement while reducing the iterations of SMO, this paper presents what we believe to be a novel mask optimization (MO) approach aimed at attaining the maximum effective CPW in every iteration. First, an optimized light source is acquired through SMO and then utilized in subsequent CPW-friendly MO steps. After optimizing all the individual mask patterns, the optimal exposure dose and anchor pattern corresponding to the maximum effective CPW are corrected. Finally, the cost function for MO is updated, and the CPW-friendly MO is executed to ultimately achieve the maximal effective CPW. In the experimental cases studied in this paper, the proposed MO technique, which incorporates corrections for exposure dose, anchor pattern, and cost functions, achieves an 8.79% improvement in CPW compared to the scenario where only mask patterns are considered during MO. The inefficiency caused by the repeated re-optimization of SMO due to insufficient CPW in each iteration is the bottleneck of the source optimization and determination process. This method can further automate the update of the MO process, achieving the maximum CPW result in each MO iteration, significantly shortening the turnaround time of the SMO-MO full procedure, and further increasing full-chip CPW.

关键词： Fourier transforms Imaging systems Light sources Lithography Optical systems Projection systems

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Surface Potential-Based Compact Model for IGZO-DRAM Enables the TCAD-to-SPICE Framework for Reliability-Aware DTCO Flow

Surface Potential-Based Compact Model for IGZO-DRAM Enables ...

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IEEE Electron Devices Technology and Manufacturing Conference (EDTM)

作者： Xufan Li Wenfeng Jiang Chen Gu Yue Zhao Di Geng Guanhua Yang Lingfei Wang Ling Li Key Lab of Fabrication Technologies for Integrated Circuits CAS Beijing China Lab of Microelectronics Devices and Integrated Technology IMECAS Beijing China

ISBN: (数字)9798331504168

ISBN: (纸本)9798331504175

With the Design-Technology Co-Optimization (DTCO) being increasingly significant in IGZO-DRAM, a surface potential-based compact model is highly required. For better understanding the disorder effects, an in-house TCAD tool is proposed to study sub-threshold properties. On this basis, a unified surface potential based compact is provided with underlying transport mechanisms for various structures. By addressing critical reliability issues, such as D2D and C2C variability, it enables the TCAD-to-SPICE framework for realizing a reliability-aware DTCO flow of IGZO-DRAM.

关键词： Electron traps Analytical models Electric potential Predictive models Surface fitting Numerical models Reliability integrated circuit modeling Three-dimensional integrated circuits Electrons

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In-materio reservoir computing based on nanowire networks:fundamental,progress,and perspective

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Materials Futures 2023年第2期2卷 79-93页

作者： Renrui Fang Woyu Zhang Kuan Ren Peiwen Zhang Xiaoxin Xu Zhongrui Wang Dashan Shang State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of Chinese Academy of SciencesBeijing 100029People’s Republic of China Department of Electrical and Electronic Engineering The University of Hong KongHong Kong 999077People’s Republic of China University of Chinese Academy of Sciences Beijing 100049People’s Republic of China

The reservoir computing(RC)system,known for its ability to seamlessly integrate memory and computing functions,is considered as a promising solution to meet the high demands for time and energy-efficient computing in the current big data landscape,compared with traditional silicon-based computing systems that have a noticeable disadvantage of separate storage and *** review focuses on in-materio RC based on nanowire networks(NWs)from the perspective of materials,extending to reservoir devices and *** common methods used in preparing nanowires-based reservoirs,including the synthesis of nanowires and the construction of networks,are firstly systematically *** physical principles of memristive and memcapacitive junctions are then ***,the dynamic characteristics of nanowires-based reservoirs and their computing capability,as well as the neuromorphic applications of NWs-based RC systems in recognition,classification,and forecasting tasks,are explicated in ***,the current challenges and future opportunities facing NWs-based RC are highlighted,aiming to provide guidance for further research.

关键词： reservoir computing nanowire networks short-term memory dynamic characteristics neuromorphic computing

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Vertical Channel-All-Around (CAA) IGZO FET with Recessed Source/Drain Structure to Improve Contact Characteristics

IEEE Electron Device Letters

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IEEE Electron Device Letters 2025年

作者： Chen, Chuanke Gu, Chen Zhao, Yue Duan, Xinlv Lu, Congyan Niu, Jiebin Zhang, Kaiping Liu, Yu Zhao, Shengjie Li, Weiwei Wu, Wanming Zhang, Chunyu Hu, Ke Wang, Shipeng Tong, Qingding Tang, Yinzhi Lu, Nianduan Geng, Di Li, Ling Institute of Microelectronics of Chinese Academy of Sciences State Key Laboratory of Fabrication Technologies for Integrated Circuits Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China

We proposed recessed source/drain(S/D) structure for vertical channel-all-around (CAA) IGZO FET to introduce contact interlayer and improve its contact characteristics. The IZO interlayer introduced between S/D and IGZO helps to reduce the contact resistance, and boosting the performance of CAA IGZO FET. The fabricated CAA IGZO FETs with 8 nm IZO interlayer show an average Ion @ Vth+1V of 32.6 μA/μm, SS of 86 mV/dec, and Vth of - 0.06 V. The Schottky barrier height qB is extracted to be reduced from 170 meV to 65 meV by introducing the contact interlayer, which confirms the improvement of contact characteristics. © 1980-2012 IEEE.

关键词： Schottky barrier diodes

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Improved Memory Window and Retention of Silicon Channel Hf0.5Zr0.5O2 FeFET by Using SiO2/HfO2/SiO2 Gate Side Interlayer

Improved Memory Window and Retention of Silicon Channel Hf0....

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Annual International Symposium on Reliability Physics

作者： Runhao Han Jia Yang Tao Hu Mingkai Bai Yajing Ding Xianzhou Shao Saifei Dai Xiaoqing Sun Junshuai Chai Hao Xu Xiaolei Wang Wenwu Wang Tianchun Ye Chinese Academy of Sciences Key Laboratory of Fabrication Technologies for Integrated Circuits Beijing Chinese Academy of Sciences Institute of Microelectronics Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798331504779

ISBN: (纸本)9798331504786

We demonstrate a Si-channel Hf 0 . 5 Zr 0 . 5 O 2 FeFET that achieves a record-high memory window (MW) of up to 19.4 V, together with improved data retention. This advancement is realized by inserting the SiO 2 /HfO 2 /SiO 2 gate interlayer between the metal gate and the ferroelectric Hf 0 . 5 Zr 0 . 5 O 2 layer. The gate interlayer effectively retains the charges injected from the metal gate. The influence of SiO 2 thickness on the reliability was investigated. Although thicker SiO 2 layer enhance the memory window, its endurance is poor. The data retention improves with increasing SiO 2 layer thickness. Furthermore, the charge trapping behaviors of gate-injected electrons and holes are asymmetric. This work provides new insights into the gate-injected charges and data retention in the FeFETs with gate interlayer.

关键词： Zirconium Hafnium Logic gates Charge carrier processes Hafnium oxide Silicon Reliability FeFETs Physics

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Laser-Induced Low Temperature Dopant Segregation Schottky Barrier Mosfet for Monolithic-3D

Laser-Induced Low Temperature Dopant Segregation Schottky Ba...

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IEEE Electron Devices Technology and Manufacturing Conference (EDTM)

作者： Feixiong Wang Yadong Zhang Jinbiao Liu Yunjiao Bao Zhiyao Wang Shuang Liu Mingzheng Ding Zhaohao Zhang Qingzhu Zhang Huaxiang Yin Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing Chinese Academy of Sciences Institute of Microelectronics Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798331504168

ISBN: (纸本)9798331504175

In this work, we present a BEOL-compatible lowtemperature (Low-T, $\leq 500^{\circ} \mathrm{C}$ ) laser-induced silicide dopant segregation source/drain (LSDS S/D) technology for Monolithic-3D integrations. A nanosecond pulse green laser was used to induce dopant segregation of Schottky S/D, therefore a sharpened interface with high Schottky Barrier and a high impurity concentration are obtained. High performance CMOS devices are achieved with Ion > 100 $\mu \mathrm{A} / \mu \mathrm{m}$ at $\mathrm{L}_{\mathrm{G}}=500 \text{nm}$ . We also demonstrate inverters, ring oscillators and logic gates, presenting an alternative fabrication scheme suitable for M3D circuit applications.

关键词： fabrication Ring oscillators Performance evaluation MOSFET Silicides Schottky barriers Ring lasers Logic gates Inverters Silicon

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A 256 Kbit Hf0.5Zr0.5O2-based FeRAM Chip with Scaled Film Thickness (sub-8nm), Low Thermal Budget (350oC), 100% Initial Chip Yield, Low Power Consumption (0.7 pJ/bit at 2V write voltage), and Prominent Endurance (>1012)

A 256 Kbit Hf0.5Zr0.5O2-based FeRAM Chip with Scaled Film Th...

引用

2023 International Electron Devices Meeting, IEDM 2023

作者： Jiang, Pengfei Jiang, Haijun Yang, Yang Tai, Lu Wei, Wei Gong, Tiancheng Wang, Yuan Xu, Pan Lv, Shuxian Wang, Boping Gao, Jianfeng Li, Junfeng Luo, Jun Yang, Jianguo Luo, Qing Liu, Ming Shandong University School of Information Science and Engineering Qingdao China Institute of Microelectronics Chinese Academy of Sciences State Key Laboratory of Fabrication Technologies for Integrated Circuits Beijing China Institute of Microelectronics Chinese Academy of Sciences Laboratory of Microelectronics Devices and Integrated Technology Beijing China Zhangjiang Lab Shanghai China

ISBN: (纸本)9798350327670

In this work, we successfully resolve the remanent polarization (Pr) degradation issue, which is caused by the thermal budget decreasing and the film thickness scaling of Hf0.5Zr0.5O2 (HZO), and co-integrate the TiN/HZO/TiN capacitors with large initial Pr and low operating voltage in the Back-End-of -Line (BEOL) of 130nm CMOS technology to provide a 256 Kbit 1T1C FeRAM chip. Firstly, we prove that the Pr degradation is caused by the increasing component of anti-ferroelectric (AFE) phase. Then, utilizing the pre-crystallization engineering and O3 treatment to the TiN bottom electrode (BE), not only the formation of t-phase is effectively suppressed, but also the required annealing temperature is reduced. The enhancement of ferroelectricity is related to the small thermal expansion of TiO2 interface layer, which can induce large tensile stress to HZO during the annealing process. Moreover, the oxidization of TiN BE can prevent it absorbing oxygen from HZO, and the reduced oxygen vacancy (Vo) defects can improve both the retention and TDDB characteristics. Based on the above optimizations, the chip demonstrates 100% initial chip yield, >150mV sense margin after 1012 write cycles, power consumption of 0.7 pJ/bit at 2V write voltage, over 1012 endurance and 10 years retention. © 2023 IEEE.

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A MONOLITHICALLY integrated MICROCANTILEVER ARRAY FOR BIOMOLECULAR DETECTION 26

A MONOLITHICALLY INTEGRATED MICROCANTILEVER ARRAY FOR BIOMOL...

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26th International Conference on Miniaturized Systems for Chemistry and Life Sciences, MicroTAS 2022

作者： Liu, Yi Lin, Cong Miao, Jiahao Yu, Xiaomei National Key Laboratory of Science and Technology on Micro/Nano Fabrication School of Integrated Circuits Peking University Beijing100871 China

ISBN: (纸本)9781733419048

In this paper, a monolithically integrated microcantilever chip consisting of a piezoresistive microcantilever array and an on-chip signal processing circuits is developed based on a SOI CMOS process. Both the piezoresistor embedded in the microcantilever and the CMOS circuit were fabricated by the single-crystal silicon of a SOI wafer, which will provide a high signal to noise ratio (SNR) for the integrated microcantilever sensor. The integrated microcantilever was functionalized by biotinylated goat anti-human Immunoglobulin G for a specific detection of IgG, and a minimum concentration of 0.8 ng/mL was detected. This technique provides a broad application prospect in biomolecule detections with high sensitivity. © 2022 MicroTAS 2022 - 26th International Conference on Miniaturized Systems for Chemistry and Life Sciences. All rights reserved.

关键词： Signal to noise ratio

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Direct Evidence of Oxygen Vacancy Generation in Whole Gate Stacks Through Multiple Electrical and Atomic-Scale Physical Methods as the Cause of Endurance Failure in FeFETs

Direct Evidence of Oxygen Vacancy Generation in Whole Gate S...

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IEEE Electron Devices Technology and Manufacturing Conference (EDTM)

作者： Xianzhou Shao Hao Xu Saifei Dai Fengbin Tian Xiaoyu Ke Jiahui Duan Min Liao Xinpei Jia Xiaoqing Sun Junshuai Chai Jun Luo Wenwu Wang Xiaolei Wang Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China Institute of Microelectronics Chinese Academy of Sciences Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798331504168

ISBN: (纸本)9798331504175

We have experimentally confirmed that the oxygen vacancy ( $\mathrm{V}_{\mathrm{O}}$ ) generation within whole gate stacks is the origin of the endurance failure in Si FeFET by multiple electrical methods and atomic-scale physical characterization techniques. Through gate leakage, lowfrequency noise, and split I-V measurements, we found that defect generation occurs in whole gate stacks and electron-hole recombination during bipolar cycling plays a dominant role. Furthermore, we determined that the type of the generated defects is $\mathrm{V}_{\mathrm{O}}$ based on scanning transmission electron microscopy (STEM) and electron energy-loss spectroscopy (EELS) characterizations.

关键词： Zirconium Pulse measurements Current measurement Hafnium Logic gates Silicon Gate leakage FeFETs Electrons Thickness measurement

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