检索结果-内蒙古大学图书馆

Effects of heavy ion irradiation on ultra-deep-submicron partially-depleted SOI devices

Journal of Semiconductors 2015年第11期36卷 39-43页

作者：武唯康安霞谭斐冯慧陈叶华刘静静张兴黄如 Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

The effects of the physical damages induced by heavy ion irradiation on the performance of partiallydepleted SOI devices are experimentally investigated. After heavy ion exposure, different degradation phenomena are observed due to the random strike of heavy ions. A decrease of the saturation current and transconductance,and an enhanced gate-induced drain leakage current are observed, which are mainly attributed to the displacement damages that may be located in the channel, the depletion region of the drain/body junction or the gate-to-drain overlap region. Further, PDSOI devices with and without body contact are compared, which reveals the differences in the threshold voltage shift, the drain-induced barrier lowing effect, the transconductance and the kink effect. The results may provide a guideline for radiation hardened design.

关键词： heavy ion displacement damages PDSOI performance degradation

来源：评论

学校读者我要写书评

暂无评论

A low-power calibration-free fractional-N digital PLL with high linear phase interpolator

A low-power calibration-free fractional-N digital PLL with h...

引用

IEEE Asian Conference on Solid-State circuits (ASSCC)

作者： Fan Yang Hangyan Guo Runhua Wang Zherui Zhang Junhua Liu Huailin Liao Key Laboratory of Microelectronic Devices and Circuits (MOE) Peking University Beijing China

ISBN: (纸本)9781509037018

This paper presents a low-complexity calibration-free digital PLL architecture. The PLL adopts a fractional frequency divider with a harmonic rejection current steering phase interpolator which is free from pre- and background-calibration. The harmonic rejection technology could improve linearity of interpolator. A simplified glitch-free control logic for fractional operation is proposed to lower architecture complexity and minimal design effort. A high frequency resolution digitally-controlled oscillator with an equivalent variable inductor is also utilized. A 2.2-GHz digital PLL has been implemented in a 55-nm CMOS technology. The frequency resolution of DCO is 1.58 kHz, and in-band phase noise of PLL is -104.4 dBc/Hz. The PLL consumes 2.43 mA from a 1.2-V supply voltage and occupies an active area of 0.216 mm 2 .

关键词： Phase locked loops Harmonic analysis Power harmonic filters Inductors Clocks Frequency conversion Detectors

来源：评论

学校读者我要写书评

暂无评论

A 51-nW 32.7-kHz CMOS relaxation oscillator with half-period pre-charge compensation scheme for ultra-low power systems

A 51-nW 32.7-kHz CMOS relaxation oscillator with half-period...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Yongan Zheng Lili Zhou Fan Tian Mingxiao He Huailin Liao Key Laboratory of Microelectronic Devices and Circuits (MOE) Peking University Beijing China

ISBN: (纸本)9781479953424

This paper presents a temperature and supply voltage variation-tolerant CMOS relaxation oscillator which is suitable for ultra-low power systems. A low-power low-cost half-period pre-charge compensation scheme is proposed to eliminate influences of the delay of the comparator and the RS latch on the frequency stability of the relaxation oscillator. In a clock period consisting of four working stages including normal charge, discharge, pre-charge and hold stage, the threshold voltage of comparators is adjusted dynamically. A 32.7-kHz relaxation oscillator with the proposed half-period pre-charge compensation scheme is implemented in a TSMC 0.18-μm CMOS process, occupying a silicon area of 0.048 mm2. Simulation results show that the proposed relaxation oscillator consumes 51-nW at room temperature from 0.6-V power supply, and temperature stability of 43.1 ppm/°C from -55 °C to 125 °C and ±0.60% frequency variation with supply voltage from 0.5 V to 1.0 V are achieved.

关键词： Oscillators CMOS integrated circuits Delays Clocks Thermal stability Circuit stability

来源：评论

学校读者我要写书评

暂无评论

Line-edge roughness induced single event transient variation in SOI Fin FETs

引用

Journal of Semiconductors 2015年第11期36卷 25-29页

作者：武唯康安霞蒋晓波陈叶华刘静静张兴黄如 Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

The impact of process induced variation on the response of SOI Fin FET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When Fin FET biased at OFF state configuration（Vgs D0, Vds DVdd/ is struck by a heavy ion, the drain collects ionizing charges under the electric field and a current pulse（single event transient, SET） is consequently formed. The results reveal that with the presence of line-edge roughness（LER）, which is one of the major variation sources in nano-scale Fin FETs, the device-to-device variation in terms of SET is observed. In this study, three types of LER are considered： type A has symmetric fin edges, type B has irrelevant fin edges and type C has parallel fin edges. The results show that type A devices have the largest SET variation while type C devices have the smallest variation. Further, the impact of the two main LER parameters,correlation length and root mean square amplitude, on SET variation is discussed as well. The results indicate that variation may be a concern in radiation effects with the down scaling of feature size.

关键词： heavy ion irradiation single event transient variation line-edge roughness SOI Fin FET

来源：评论

学校读者我要写书评

暂无评论

Neuromorphic Computing: Ion Gated Synaptic Transistors Based on 2D van der Waals Crystals with Tunable Diffusive Dynamics (Adv. Mater. 21/2018)

引用

Advanced Materials 2018年第21期30卷

作者： Jiadi Zhu Yuchao Yang Rundong Jia Zhongxin Liang Wen Zhu Zia Ur Rehman Lin Bao Xiaoxian Zhang Yimao Cai Li Song Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing 100871 China National Synchrotron Radiation Laboratory CAS Center for Excellence in Nanoscience University of Science and Technology of China Hefei Anhui 230029 China CAS Key Laboratory of Standardization and Measurement for Nanotechnology CAS Center for Excellence in Nanoscience National Center for Nanoscience and Technology Beijing 100190 China

来源：评论

学校读者我要写书评

暂无评论

Vertical Transistors: Analog Circuit Applications Based on Ambipolar Graphene/MoTe2Vertical Transistors (Adv. Electron. Mater. 3/2018)

引用

Advanced Electronic Materials 2018年第3期4卷

作者： Chen Pan Yajun Fu Jiaxin Wang Junwen Zeng Guangxu Su Mingsheng Long Erfu Liu Chenyu Wang Anyuan Gao Miao Wang Yu Wang Zhenlin Wang Shi-Jun Liang Ru Huang Feng Miao National Laboratory of Solid State Microstructures School of Physics Collaborative Innovation Center of Advanced Microstructures Nanjing University Nanjing 210093 China School of Material Science and Engineering Southwest University of Science and Technology Mianyang 621010 China Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing 100871 China

来源：评论

学校读者我要写书评

暂无评论

A novel insight into transient behaviors of diode-triggered SCRs under VF-TLP testing by 2D/3D simulations

A novel insight into transient behaviors of diode-triggered ...

引用

IEEE International Nanoelectronics Conference (INEC)

作者： Lizhong Zhang Yuan Wang Yandong He Key Laboratory of Microelectronic Devices and Circuits (MoE) Institute of Microelectronics Peking University Beijing

Transient behaviors of the diode-triggered silicon controlled rectifiers (DTSCRs) under very-fast transmission line pulse (VF-TLP) testing are investigated in this paper. The underlying physics needs to be comprehensively investigated and 2D/3D device simulations are well performed and compared. Analysis uncovers that the turn-on process of intrinsic SCR is ascribed to Darlington effect as well as junction breakdown.

关键词： Thyristors Junctions Electrostatic discharges Testing Anodes Performance evaluation

来源：评论

学校读者我要写书评

暂无评论

Enhanced recrystallization of ultra-thin α-silicon film by 2-D confined lattice regrowth

Enhanced recrystallization of ultra-thin α-silicon film by ...

引用

IEEE International Nanoelectronics Conference (INEC)

作者： Hao Zhang Ming Li Gong Chen Yuancheng Yang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

In this paper, the improved recrystallization of ultra-thin amorphous silicon (α-Si) film was realized by two-dimensionally confined lattice regrowth with normal rapid thermal annealing process. By experimental investigation, the α-Si films with thickness of 400 Å were found to be recrystallized even at 850°C for only 35s rapid thermal annealing (RTA). With capped Si 3 N 4 layer, the lattice regrowth was confined more strictly to along the film plane so that smoother and higher-quality polycrystalline silicon film was obtained which is suitable for future monolithic three dimensional (3D) stacked integration processes.

关键词： Films Annealing Lattices Rough surfaces Surface roughness Three-dimensional displays Grain size

来源：评论

学校读者我要写书评

暂无评论

A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic

A novel low-power and high-speed dual-modulus prescaler base...

引用

International Symposium on circuits and Systems

作者： Song Jia Ziyi Wang Zijin Li Yuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 Beijing China

ISBN: (纸本)9781479953424

A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock (E-TSPC) scheme is presented. By restricting the short-circuit current in noncritical branchs, the design reduces the major source of power dissipation in E-TSPC scheme. The presented design enhances the maximum working frequency with shorter critical path and lower load capacitances. Simulation results in SMIC 40nm process show that compared with referenced E-TSPC based designs at least 61.2% (divide-by-2) and 41.1% (divide-by-3) reduction in power delay product (PDP) can be achieved by the proposed design.

关键词： short-circuit power E-TSPC prescaler critical path

来源：评论

学校读者我要写书评

暂无评论

Layout dependent BTI and HCI degradation in nano CMOS technology: A new time-dependent LDE and impacts on circuit at end of life

Layout dependent BTI and HCI degradation in nano CMOS techno...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Pengpeng Ren Runsheng Wang Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)9781509003211

In this paper, the newly-found time-dependent layout dependent effects (LDE) due to layout dependency of device aging is presented. BTI and HCI degradation in nanoscale HKMG devices exhibits evident layout dependency, which will significantly complicate the circuit design. With the analysis on circuit level, the time-dependent LDE should be considered to ensure enough design margin, especially at end of life. This work is helpful to design-technology co-optimization at nanoscale nodes.

关键词： Layout Delays Aging Human computer interaction Degradation Nanoscale devices Reliability

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：