In this paper, several techniques which relax circuit requirements of building blocks are presented to effectively realize wideband high-resolution cascade sigma-delta modulator. Three cascade structures have been pro...
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In this paper, several techniques which relax circuit requirements of building blocks are presented to effectively realize wideband high-resolution cascade sigma-delta modulator. Three cascade structures have been proposed in this paper. First, a MASH 2-2 with feed-forward topology in both stages has been explained to obtain low-distortion property and remove subtraction Second, a flexible SMASH 2-2 has been proposed to choose appropriate coefficients for different requirements. Third, a SMASH 2-2 with feed-forward quantization noise self-coupled structure has been displayed to cancel quantization error of the preceding stage totally. Detailed simulation results and comparisons demonstrate the performance of these topologies.
This paper presents a 14-bit digital-to-analog converter (DAC) with pipelined dynamic element matching to eliminate signal-dependent distortions and achieve good linearity at high sampling frequencies. A return-to-zer...
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This paper presents a 14-bit digital-to-analog converter (DAC) with pipelined dynamic element matching to eliminate signal-dependent distortions and achieve good linearity at high sampling frequencies. A return-to-zero output stage is developed to enhance the dynamic linearity and increase the output impedance of current sources. And a novel current source array is employed to eliminate systematic and graded errors. The spurious-free dynamic range is 80.9dB at 312MS/s with a 150MHz input. The DAC is implemented in a 0.13-μm CMOS process, and consumes 48mW at 1.2-V power supply and 312MS/s.
This paper presents a predictive electrostatic capacitance and resistance compact model of multiple gate MOSFET with cylindrical conducting channels, taking into account parasitic effects, quantum confinement and quas...
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ISBN:
(纸本)9781424457977
This paper presents a predictive electrostatic capacitance and resistance compact model of multiple gate MOSFET with cylindrical conducting channels, taking into account parasitic effects, quantum confinement and quasi-ballistic effects. The model incorporates the dependence of channel length, gate height and width, gate-to-contact spacing, nanowire size, multiple channels, as well as 1-D ultra-narrow source/drain extension (SDE) doping profile. The proposed non-iterative electrostatic model is successfully verified, and can be used to predict nanowire-based circuit performance. Based on the analytical model, we can further examine which parasitic components are affecting the delay. Results revealed that Qside. Cof, Rsd RQ are dominant factors and should be treated as a major design concern. Among all the parameters, Lsd Tg and Ndop are essentially important in parasitic design optimization. By selectively modifying these parameters, parasitic effect is evidently reduced.
In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic pr...
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ISBN:
(纸本)9781424457977
In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic properties, source/drain series resistance (RSD), and driving current. The SDE-RDF induced variations of threshold voltage (Vth) and DIBL in SNWTs with different diameters are found to be modest and decrease as the diameters down-scale. However, SDE-RDF induced RSd variation in SNWTs is enhanced by abnormal DDA effects, which aggravates the drive current variations with the downscaling of SNWT diameter. The results also show that Vth is the dominant factor in ON/OFF current ratio variation while RSd dominates that of ON current. The tradeoff between RSd and Vth dominant current variations is discussed to give some guidelines for SDE-RDF-aware design in SNWTs.
A novel LDMOS-SCR device for electrostatic discharge protection of power device is presented. The device is able to be fabricated in SOI 40V LDMOS process without any extra mask. Due to the new structure, a proper and...
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ISBN:
(纸本)9781424457977
A novel LDMOS-SCR device for electrostatic discharge protection of power device is presented. The device is able to be fabricated in SOI 40V LDMOS process without any extra mask. Due to the new structure, a proper and controllable triggering voltage and fine heat dissipation capability are achieved.
Voltage pulse dependent resistive switching behavior during SET process in HfO2-based RRAM device is investigated. When a resistor is connected in series to RRAM during the SET process, the resistance uniformity can b...
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Voltage pulse dependent resistive switching behavior during SET process in HfO2-based RRAM device is investigated. When a resistor is connected in series to RRAM during the SET process, the resistance uniformity can be improved. Voltage pulse controlled resistance states were observed. This behavior may provide the new application with the new function circuits.
A CMOS ASIC has been designed and implemented for readout and control of MEMS vibratory gyroscopes. A low noise design is achieved by using the technique of sinusoidal chopper stabilization with a chopping frequency o...
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In summary, a novel RRAM with the structure of Cu/Si x O y N z /W was first fabricated and its characteristics are thoroughly investigated. The new device exhibited low switching voltages and low reset currents, demon...
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In summary, a novel RRAM with the structure of Cu/Si x O y N z /W was first fabricated and its characteristics are thoroughly investigated. The new device exhibited low switching voltages and low reset currents, demonstrating its potential for low-power applications. Repeatable unipolar resistive switching characteristics in terms of high off/on resistance ratio and good retention capability were observed. The switching mechanism of the device was analyzed and can be explained by the formation and rupture of vacancy filaments.
We calculate valence band structures and transport property of HfO 2 gate dielectric surrounded Ge (110) nanowire with a radial force at the boundary of the insulator. The radial force pushes the valence subbands dow...
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ISBN:
(纸本)9781424435432;9781424435449
We calculate valence band structures and transport property of HfO 2 gate dielectric surrounded Ge (110) nanowire with a radial force at the boundary of the insulator. The radial force pushes the valence subbands downwards. Most of hole effective masses of top five subbands decrease and densities of states' peaks move down as the force increases. The hole mobility in Ge (110) NW significantly increases with higher force values.
This paper presents a novel mixed-voltage I/O buffer without an extra dual-oxide CMOS *** mixed-voltage I/O buffer with a simplified circuit scheme can overcome the problems of leakage current and gateoxide reliabilit...
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This paper presents a novel mixed-voltage I/O buffer without an extra dual-oxide CMOS *** mixed-voltage I/O buffer with a simplified circuit scheme can overcome the problems of leakage current and gateoxide reliability that the conventional CMOS I/O buffer *** design is realized in a 0.13-μm CMOS process and the simulation results show a good performance increased by ~34% with respect to the product of power consumption and speed.
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