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Predictive Modeling of Capacitance and Resistance in Gate-all-around Cylindrical Nanowire MOSFETs for Parasitic Design Optimization

Predictive Modeling of Capacitance and Resistance in Gate-al...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Qiumin Xu Jibin Zou Jieyin Luo Runsheng Wang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9781424457977

This paper presents a predictive electrostatic capacitance and resistance compact model of multiple gate MOSFET with cylindrical conducting channels, taking into account parasitic effects, quantum confinement and quasi-ballistic effects. The model incorporates the dependence of channel length, gate height and width, gate-to-contact spacing, nanowire size, multiple channels, as well as 1-D ultra-narrow source/drain extension (SDE) doping profile. The proposed non-iterative electrostatic model is successfully verified, and can be used to predict nanowire-based circuit performance. Based on the analytical model, we can further examine which parasitic components are affecting the delay. Results revealed that Qside. Cof, Rsd RQ are dominant factors and should be treated as a major design concern. Among all the parameters, Lsd Tg and Ndop are essentially important in parasitic design optimization. By selectively modifying these parameters, parasitic effect is evidently reduced.

关键词： Quantum capacitance Logic gates Delay Resistance Solid modeling Analytical models

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Study of LDMOS-SCR: A High Voltage ESD Protection Device

Study of LDMOS-SCR: A High Voltage ESD Protection Device

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Peng Zhang Yuan Wang Song Jia Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

A novel LDMOS-SCR device for electrostatic discharge protection of power device is presented. The device is able to be fabricated in SOI 40V LDMOS process without any extra mask. Due to the new structure, a proper and... 详细信息

ISBN: (纸本)9781424457977

关键词： electrostatic discharge protection triggering voltage HEAT DISSIPATION High Voltage energy component LDMOS

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Impacts of Diameter-Dependent Annealing on S/D Extension Random Dopant Fluctuations in Silicon Nanowire MOSFETs

Impacts of Diameter-Dependent Annealing on S/D Extension Ran...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Tao Yu Runsheng Wang Wei Ding Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9781424457977

In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic properties, source/drain series resistance (RSD), and driving current. The SDE-RDF induced variations of threshold voltage (Vth) and DIBL in SNWTs with different diameters are found to be modest and decrease as the diameters down-scale. However, SDE-RDF induced RSd variation in SNWTs is enhanced by abnormal DDA effects, which aggravates the drive current variations with the downscaling of SNWT diameter. The results also show that Vth is the dominant factor in ON/OFF current ratio variation while RSd dominates that of ON current. The tradeoff between RSd and Vth dominant current variations is discussed to give some guidelines for SDE-RDF-aware design in SNWTs.

关键词： Nanowire Diameter drive current digital differential analyzers bis(p-chlorophenyl)acetic acid annealing Silicon VOLTAGE Random

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Pulse Voltage Dependent Resistive Switching Behaviors of HfO2-Based RRAM

Pulse Voltage Dependent Resistive Switching Behaviors of HfO...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Bin Gao Bing Chen Yuansha Chen Lifeng Liu Xiaoyan Liu Ruqi Han Jinfeng Kang Institute of Microelectronics Peking University & Key Laboratory of Microelectronic Devices and Circuits Ministry of Education Beijing 100871 China

Voltage pulse dependent resistive switching behavior during SET process in HfO2-based RRAM device is investigated. When a resistor is connected in series to RRAM during the SET process, the resistance uniformity can be improved. Voltage pulse controlled resistance states were observed. This behavior may provide the new application with the new function circuits.

关键词： Resistance Voltage control Switches Resistors Tin Process control

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A VCO sub-band selection circuit for fast PLL calibration

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Journal of Semiconductors 2009年第8期30卷 153-155页

作者：宋颖王源贾嵩赵宝瑛 Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of MicroelectronicsPeking University

A novel voltage controlled oscillator （VCO） sub-band selection circuit to achieve fast phase locked loop （PLL） calibration is presented, which reduces the calibration time by measuring the period difference directly and accomplishing an efficient search for an optimum VCO sub-band. The sub-band selection circuit was implemented in a 0.18 μm CMOS logic process with a PLL using an 8 sub-band VCO. The measured calibration time is less than 3 μs in a VCO frequency range from 600 MHz to 2 GHz. The proposed circuit consumes 0.64 mA at most.

关键词： PLL VCO calibration

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A novel nitrogen-doped SiOx resistive switching memory with low switching voltages

A novel nitrogen-doped SiOx resistive switching memory with ...

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IEEE Silicon Nanoelectronics Workshop (SNW)

作者： Dejin Gao Lijie Zhang Ru Huang Runsheng Wang Dongmei Wu Yongbian Kuang Yu Tang Zhe Yu Albert Z. H. Wang Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China Department of Electrical Engineering University of California Riverside CA USA

In summary, a novel RRAM with the structure of Cu/Si x O y N z /W was first fabricated and its characteristics are thoroughly investigated. The new device exhibited low switching voltages and low reset currents, demonstrating its potential for low-power applications. Repeatable unipolar resistive switching characteristics in terms of high off/on resistance ratio and good retention capability were observed. The switching mechanism of the device was analyzed and can be explained by the formation and rupture of vacancy filaments.

关键词： Copper Resistance Switches Nitrogen Temperature Electrodes Voltage measurement

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Influence of boundary force on the performance of gate-all-around Ge (110) NW FETs with HfO2 gate insulator

Influence of boundary force on the performance of gate-all-a...

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IEEE International Nanoelectronics Conference (INEC)

作者： Honghua Xu Xiaoyan Liu Gang Du Yuhui He Chun Fan Ruqi Han Jinfeng Kang Institute of Microelectronics Key Laboratory of Microelectronic Devices and Circuits Ministry of Education Peking University Beijing China Institute of Microelectronics Peking University Beijing China Key Laboratory of Nanofabrication and Novel Devices Integration Technology Institute of Microelectronics Chinese Academy and Sciences Beijing China Computer Center Peking University Beijing China

ISBN: (纸本)9781424435432;9781424435449

We calculate valence band structures and transport property of HfO 2 gate dielectric surrounded Ge (110) nanowire with a radial force at the boundary of the insulator. The radial force pushes the valence subbands downwards. Most of hole effective masses of top five subbands decrease and densities of states' peaks move down as the force increases. The hole mobility in Ge (110) NW significantly increases with higher force values.

关键词： FETs Hafnium oxide Dielectrics and electrical insulation Capacitive sensors Effective mass Nanoscale devices Electrodes Lattices Voltage High-K gate dielectrics

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Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit

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Journal of Semiconductors 2009年第12期30卷 128-132页

作者：刘振贾嵩王源吉利久张兴 Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter （ADC） A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm^2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.

关键词： analog-to-digital converter low power fully-folding mixed-averaging distributed T/H circuit bit synchronization

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Novel mixed-voltage I/O buffer with thin-oxide CMOS transistors

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Journal of Semiconductors 2009年第7期30卷 83-85页

作者：俞波王源贾嵩张钢刚 Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

This paper presents a novel mixed-voltage I/O buffer without an extra dual-oxide CMOS *** mixed-voltage I/O buffer with a simplified circuit scheme can overcome the problems of leakage current and gateoxide reliability that the conventional CMOS I/O buffer *** design is realized in a 0.13-μm CMOS process and the simulation results show a good performance increased by ～34% with respect to the product of power consumption and speed.

关键词： mixed-voltage I/O buffer multi-power domain thin-oxide CMOS

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Design and test results of a low-noise readout integrated circuit for high-energy particle detectors

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Nuclear Science and Techniques 2010年第1期000卷

作者： ZHANG Mingming CHEN Zhongjian ZHANG Yacong LU Wengao JI Lijiu Key Laboratory of Microelectrnic Devices and Circuits Institule of Microelectronics Peking University Beijing 100871 China

A low-noise readout integrated circuit for high-energy particle detector is presented. The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source ***-time semi-Gaussian filter is chosen to avoid switch noise. The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application. The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology. Test results show the functions of the readout integrated circuit are correct. The equivalent noise charge with no detector connected is 500-700 e in the typical mode, the gain is tunable within 13-130 mV/fC and the peaking time varies from 0.7 to 1.6 μs, in which the average gain is about 20.5 mV/fC, and the linearity reaches 99.2%.

关键词： High-energy particle detectors Readout circuit Low noise ASIC

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