A readout integrated circuit for high energy particle detectors is presented. The circuit designed is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper with four selectable peaking time, and an output sta...
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In this paper, we demonstrate a Monte Carlo simulator for ambipolar Schottky barrier MOSFETs which includes tunneling and thermal emission of electrons and holes and the appropriate treatment of carrier transport at n...
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Design of a CMOS readout circuit for 160x120 format microcantilever infrared FPAs with snapshot integration is presented in this paper. The pixel pitch is 50m and capacitive trans-impedance amplifier is used in pixel ...
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作者:
牛旭东李博宋岩张立宁何进Micro and Nano Electric Device and Integrated Group
The Key Laboratory of Integrated MicrosystemsPeking University Shenzhen Graduate School TSRC
Key Laboratory of MicroelectronicsDevices and Circuits of Ministry of EducationSchool of Electronics and Computer SciencePeking University
This paper presents the benchmark test results on the symmetry and continuity characteristics between BSIM4 from Berkeley and ULTRA-BULK from Peking University. It is shown that the industry standard model BSIM4 has a...
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This paper presents the benchmark test results on the symmetry and continuity characteristics between BSIM4 from Berkeley and ULTRA-BULK from Peking University. It is shown that the industry standard model BSIM4 has a series of the shortcomings of the continuity and symmetry, such as the charge, high-order current derivatives, and the trans-capacitances while the latest advanced surface-potential based MOSFET compact model, ULTRA-BULK, demonstrates all necessary continuity and symmetry characteristics, which are very important for analog and RF circuit design.
In this paper, we investigate the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) on deep sub-micron pMOSFETs. It is found that the high temperature of the NBT stress ind...
In this paper, we investigate the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) on deep sub-micron pMOSFETs. It is found that the high temperature of the NBT stress induces an annealing effect by removing part of the radiation-induced positive charges. If we choose a relatively low temperature to avoid the annealing effect, a remarkable radiation acceleration effect on device degradation is observed and the lifetime of pMOSFETs significantly reduces due to more radiation-induced new hole traps in the oxide. However, the acceleration effect seems independent of the oxide electric field during NBT stress. The work in this paper indicates that it is important to choose proper NBT stress conditions if we use NBTI to predict the lifetime of the pMOSFETs which operate in the radiation environments.
Double gate SBFET with asymmetric barrier heights at source/drain and the symmetric DG-SBFET are simulated. A comparative study between them is made. We have found that the DG-ASBFET is more appropriate for LOP and LS...
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A readout integrated circuit (ROIC) for uncooled microcantilever infrared focal plane arrays (IRFPAs) based on capacitive readout is proposed. The ROIC is optimized according to noise modeling and analysis to reduce n...
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The impacts of three different strain configurations on both DC and RF performance of n-type silicon nanowire transistors (n-SNWTs) are investigated. It is found that the longitudinal tensile strain is the most effici...
The impacts of three different strain configurations on both DC and RF performance of n-type silicon nanowire transistors (n-SNWTs) are investigated. It is found that the longitudinal tensile strain is the most efficient in improving the driving current and RF performance of n-SNWTs under the same stress value. In addition, the transverse compressive strain is also beneficial to the performance improvement, and can be combined in the stress engineering. Particularly, transverse biaxial compressive strain can effectively enhance the driving current, and at the same time slightly decrease the off-current of n-SNWT, which is beneficial for high speed and low power design. The results indicate that, due to the unique feature of gate-all-around 1D structure, the strain design in SNWTs, especially the combination of longitudinal strain and transverse strain, can be specially optimized for better device performance.
Dynamic circuit is suitable for high-speed application, but often suffers from noise related reliability problems which become increasingly prominent as the technology are entering into the scores of nano meter era. T...
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Dynamic circuit is suitable for high-speed application, but often suffers from noise related reliability problems which become increasingly prominent as the technology are entering into the scores of nano meter era. This paper presented a new dynamic circuit scheme, which could achieve higher noise margin without sacrificing much power consumption and delay time. This design achieves a higher noise margin (1.2 V) by finely tuning the transistor size. The effectiveness of new scheme is demonstrated in both NMOS series and parallel circuits. The simulation result shows that, compared with other published work, the proposed structure has the highest noise margin for the same power-delay product (PDP) 1 .
For the radial boundary force induced in the process, the strain energy distribution and strain tensor components in Ge (110) nanowire (NW) are calculated by finite element method. Based on the strain distribution, we...
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