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An AND-type 1T-FeFET array with robust write and read operations

Science China(Information Sciences) 2025年第2期68卷 395-396页

作者： Jiacheng XU Jiayi ZHAO Hongrui ZHANG Haoji QIAN Jiani GU Bowen CHEN Gaobo LIN Rongzong SHEN Xinda SONG Huan LIU Yian DING Minglei MA Miaomiao ZHANG Xiao YU Bing CHEN Ran CHENG Gaobo XU Huaxiang YIN Yan LIU Jiajia CHEN Chengji JIN Genquan HAN Hangzhou Institute of Technology and School of Microelectronics Xidian University Zhejiang Lab College of Integrated Circuits Zhejiang University Key Laboratory of Microelectronics Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of Sciences

HfO2-based ferroelectric field-effect transistor（Fe FET） has become a promising solution for next-generation embedded non-volatile memory（NVM） owing to its complementary metal-oxide-semiconductor（CMOS） compatibility,small footprint, high performance, and non-destructive readout [1]. Recent research of HfO2-based Fe FET has focused on the device operation mechanisms as well as reliability issues such as the interplay between polarization switching and charge trapping/detrapping [2], read-after-write latency [3] and endurance degradation [4].

关键词： Ferroelectric devices

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Experimental investigation of a novel junction-modulated hetero-layer tunnel FET with the striped gate for low power applications

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Science China(Information Sciences) 2023年第6期66卷 313-314页

作者： Zhongxin LIANG Yang ZHAO Kaifeng WANG Jieyin ZHANG Jianjun ZHANG Ming LI Ru HUANG Qianqian HUANG Key Laboratory of Microelectronics Devices and Circuits (MOE) School of Integrated CircuitsPeking University Key Laboratory of Nanophysics and Devices Institute of PhysicsChinese Academy of Sciences Beijing Advanced Innovation Center for Integrated Circuits

Silicon-based tunneling field effect transistor(TFET) with a band-to-band tunneling mechanism has been widely studied due to its ultra-steep subthreshold swing(SS),ultralow leakage current(Ioff),and good complementary...

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A centripetal collection image sensor(CCIS) based on back gate modulation achieving 1T submicron pixel

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Science China(Information Sciences) 2022年第4期65卷 282-284页

作者： Liqiao LIU Guihai YU Gang DU Xiaoyan LIU Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

Dear editor,Image sensors have been rapidly developed for decades and widely used in many different fields [1, 2]. To achieve high resolution, the pixel size has been scaled down to 1 μm for mass production [3]. Nevertheless, the pixel size has to be further reduced to meet the growing demand for higher resolution. In CMOS image sensor(CIS), the pixel is composed of a photodiode, reset transistor,

关键词： Image sensor submicron pixel back gate modulation pixel crosstalk Silicon on insulator

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CMN: a co-designed neural architecture search for efficient computing-in-memory-based mixture-of-experts

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Science China(Information Sciences) 2024年第10期67卷 100-114页

作者： Shihao HAN Sishuo LIU Shucheng DU Mingzi LI Zijian YE Xiaoxin XU Yi LI Zhongrui WANG Dashan SHANG Department of Electrical and Electronic Engineering The University of Hong Kong ACCESS-AI Chip Center for Emerging Smart Systems InnoHK Centers Key Lab of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Laboratory of Microelectronics Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of Sciences University of Chinese Academy of Sciences School of Microelectronics Southern University of Science and Technology

Artificial intelligence(AI) has experienced substantial advancements recently, notably with the advent of large-scale language models(LLMs) employing mixture-of-experts(MoE) techniques, exhibiting human-like cognitive skills. As a promising hardware solution for edge MoE implementations, the computing-in-memory(CIM) architecture collocates memory and computing within a single device, significantly reducing the data movement and the associated energy consumption. However, due to diverse edge application scenarios and constraints, determining the optimal network structures for MoE, such as the expert's location,quantity, and dimension on CIM systems remains elusive. To this end, we introduce a software-hardware co-designed neural architecture search(NAS) framework, CIM-based MoE NAS(CMN), focusing on identifying a high-performing MoE structure under specific hardware constraints. The results of the NYUD-v2 dataset segmentation on the RRAM(SRAM) CIM system reveal that CMN can discover optimized MoE configurations under energy, latency, and performance constraints, achieving 29.67×(43.10×) energy savings,175.44×(109.89×) speedup, and 12.24× smaller model size compared to the baseline MoE-enabled Visual Transformer, respectively. This co-design opens up an avenue toward high-performance MoE deployments in edge CIM systems.

关键词： mixture-of-experts computing-in-memory neural architecture search resistive random-access memory static random-access memory

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Physical investigation of subthreshold swing degradation behavior in negative capacitance FET

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Science China(Information Sciences) 2022年第6期65卷 241-246页

作者： Mengxuan YANG Qianqian HUANG Kaifeng WANG Chang SU Liang CHEN Yangyuan WANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of MicroelectronicsPeking University Beijing Laboratory of Future IC Technology and Science Peking University

Power consumption has become one of the bottlenecks limiting the future development of integrated circuits. Tunnel FETs(TFETs) and negative capacitance FETs(NCFETs) can break the subthreshold swing limitation(60 mV/dec at room temperature) of conventional metal-oxide-semiconductor field-effect transistor(MOSFET) to reduce the operating voltage and thus power consumption. However, induced by the band-to-band tunneling mechanism, TFETs have a subthreshold swing degradation issue and relatively low ON current. Although NCFETs with ferroelectric/dielectric gate stack can theoretically maintain a high ON current comparable to conventional MOSFET, the physical origin of sub-60 SS is controversial and the mechanism of switching behavior in NCFET is still not clear. In this work, by experimentally investigating the whole negative differential capacitance process and its gate voltage amplification coefficient, an intrinsic issue of SS degradation with increased gate voltage is also found in NCFET for the first time. Based on the physical investigation and simulation results, it is shown that the intrinsic SS degradation in NCFET is resulting from the instant dielectric polarization response. Both the decrease of dielectric thickness and the increase of dielectric constant may lead to the severer SS degradation, which is not favorable for scaled NCFETs.

关键词： ferroelectric negative differential capacitance effect polarization low power voltage amplification

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Experimental investigation of the gate voltage range of negative differential capacitance in ferroelectric transistors

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Science China(Information Sciences) 2022年第6期65卷 277-278页

作者： Mengxuan YANG Qianqian HUANG Chang SU Liang CHEN Yangyuan WANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of MicroelectronicsPeking University Beijing Laboratory of Future IC Technology and Science Peking University

Dear editor,Recently, ferroelectric(FE)-based negative capacitance FET(NCFET) with ferroelectric/dielectric(FE/DE) gate stack has attracted extensive attention due to its capability of sub-60 mV/dec subthreshold swing... 详细信息

关键词： Ferroelectric Negative differential capacitance effect Polarization Low power Subthreshold swing

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Layout dependence of total-ionizing-dose response in 65-nm bulk Si pMOSFET

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Science China(Information Sciences) 2021年第2期64卷 271-272页

作者： Zhexuan REN Xia AN Gensong LI Xing ZHANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

Dear editor,Strain technology has become a common solution in the semiconductor manufacturing industry since 90-nm technology node to overcome the severe carrier mobility degradation of nanoscale microelectronic devices [1]. Since layout may affect the stress distribution, layout dependent effect(LDE)becomes a serious issue in advanced technology nodes.

关键词： radiation TID LDE 65nm PMOS SA

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A Fully BEOL-compatible (300°C Annealing) IGZO FeFET with Ultra-high Memory Window (10V) and Prominent Endurance (109)

A Fully BEOL-compatible (300°C Annealing) IGZO FeFET with U...

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2024 IEEE International Electron devices Meeting, IEDM 2024

作者： Xu, Pan Jiang, Pengfei Yang, Yang Peng, Xueyang Wei, Wei Gong, Tiancheng Wang, Yuan Long, Xiao Niu, Jiebin Xu, Zhongguang Zhu, Chenxin Wu, Zhenhua Luo, Qing Liu, Ming Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China University of Science and Technology of China Anhui Hefei China

ISBN: (纸本)9798350365429

HfO2-based FeFET paves the way for the next generation NVM thecnology, however, demands for high memory window (MW) and roubust reliability (especially the endurance) cannot be combined in the current reported devices, and the contradiction of high MW and low thermal budget (aiming for BEOL compatibility) also needs to be solved. In this work, we propose an integrated ferroelectric (FE) Hf0.5Zr0.5O2 (HZO) and amorphous In-Ga-Zn-O (a- IGZO) channel FeFET with a maximum 10V MW and prominent endurance up to 109. Workfunction (WF) engineering is utilized to regualtethe intrinsic Vt to improve the PGM/ERS efficiency with full-loop polarization switching, and the adopted Mo gate can effectively reduce the thermal budget to 300°Censuringa fully BEOL compatibility. Then with O3-plasma treatment to the gate electrode, the introduced tunneling layer can futher improve the MW by gate charge injection. The demonstrated FeFET shows great 3-bit/cell storage ability without states overlapping, high Ion/Ioff ratio (>107), as well as great linearity and high Gmax/Gmin (286) during synaptic weight modulation. © 2024 IEEE.

关键词： Budget control

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A 256 Kbit Hf0.5Zr0.5O2-based FeRAM Chip with Scaled Film Thickness (sub-8nm), Low Thermal Budget (350oC), 100% Initial Chip Yield, Low Power Consumption (0.7 pJ/bit at 2V write voltage), and Prominent Endurance (>1012)

A 256 Kbit Hf0.5Zr0.5O2-based FeRAM Chip with Scaled Film Th...

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2023 International Electron devices Meeting, IEDM 2023

作者： Jiang, Pengfei Jiang, Haijun Yang, Yang Tai, Lu Wei, Wei Gong, Tiancheng Wang, Yuan Xu, Pan Lv, Shuxian Wang, Boping Gao, Jianfeng Li, Junfeng Luo, Jun Yang, Jianguo Luo, Qing Liu, Ming Shandong University School of Information Science and Engineering Qingdao China Institute of Microelectronics Chinese Academy of Sciences State Key Laboratory of Fabrication Technologies for Integrated Circuits Beijing China Institute of Microelectronics Chinese Academy of Sciences Laboratory of Microelectronics Devices and Integrated Technology Beijing China Zhangjiang Lab Shanghai China

ISBN: (纸本)9798350327670

In this work, we successfully resolve the remanent polarization (Pr) degradation issue, which is caused by the thermal budget decreasing and the film thickness scaling of Hf0.5Zr0.5O2 (HZO), and co-integrate the TiN/HZO/TiN capacitors with large initial Pr and low operating voltage in the Back-End-of -Line (BEOL) of 130nm CMOS technology to provide a 256 Kbit 1T1C FeRAM chip. Firstly, we prove that the Pr degradation is caused by the increasing component of anti-ferroelectric (AFE) phase. Then, utilizing the pre-crystallization engineering and O3 treatment to the TiN bottom electrode (BE), not only the formation of t-phase is effectively suppressed, but also the required annealing temperature is reduced. The enhancement of ferroelectricity is related to the small thermal expansion of TiO2 interface layer, which can induce large tensile stress to HZO during the annealing process. Moreover, the oxidization of TiN BE can prevent it absorbing oxygen from HZO, and the reduced oxygen vacancy (Vo) defects can improve both the retention and TDDB characteristics. Based on the above optimizations, the chip demonstrates 100% initial chip yield, >150mV sense margin after 1012 write cycles, power consumption of 0.7 pJ/bit at 2V write voltage, over 1012 endurance and 10 years retention. © 2023 IEEE.

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First Demonstration of a Design Methodology for Highly Reliable Operation at High Temperature on 128kb 1T1C FeRAM Chip

First Demonstration of a Design Methodology for Highly Relia...

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2023 IEEE Symposium on VLSI Technology and circuits, VLSI Technology and circuits 2023

作者： Gong, Tiancheng Xu, Lihua Wei, Wei Jiang, Pengfei Yuan, Peng Nie, Bowen Huang, Yuanquan Wang, Yuan Yang, Yang Gao, Jianfeng Li, Junfeng Luo, Jun Wang, Lingfei Yang, Jianguo Luo, Qing Li, Ling Chung, Steve S. Liu, Ming Institute of Microelectronics Chinese Academy of Sciences State Key Laboratory of Fabrication Technologies for Integrated Circuits Beijing China Institute of Microelectronics Chinese Academy of Sciences Laboratory of Microelectronics Devices and Integrated Technology Beijing China Institute of Electronics National Yang Ming Chiao Tung University Taiwan

ISBN: (纸本)9784863488069

In achieving a reliable operation of FRAM arrays at high temperature (300K-400K), we provide an optimized operation design methodology considering the temperature effect on 128kb ITIC FRAM chip for the first time. Firstly, we found that the conventional voltage selection scheme in ITIC FRAM array is not applicable at high temperature since the Pr value read by low voltage decreases at high temperature, leading to a poor yield. Then, the mechanism of Pr degradation under high temperature is systematically investigated through material characterizations and electrical measurements. It was found that the increase of the internal electric field (Ebias) caused by electron de-trapping mainly contributes to the Pr degradation. Moreover, a KMC model considering Ebias is developed, and the optimum voltage, which can mitigate the temperature effect from 300K-400K, is predicted. This predicted voltage is finally validated on 128kb ITIC FeRAM chip, and excellent properties including non-volatile (150°C >106s) and high endurance (>1011) under the predicted voltage are also demonstrated. © 2023 JSAP.

关键词： Temperature

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