This paper presents a predictive electrostatic capacitance and resistance compact model of multiple gate MOSFET with cylindrical conducting channels, taking into account parasitic effects, quantum confinement and quas...
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ISBN:
(纸本)9781424457977
This paper presents a predictive electrostatic capacitance and resistance compact model of multiple gate MOSFET with cylindrical conducting channels, taking into account parasitic effects, quantum confinement and quasi-ballistic effects. The model incorporates the dependence of channel length, gate height and width, gate-to-contact spacing, nanowire size, multiple channels, as well as 1-D ultra-narrow source/drain extension (SDE) doping profile. The proposed non-iterative electrostatic model is successfully verified, and can be used to predict nanowire-based circuit performance. Based on the analytical model, we can further examine which parasitic components are affecting the delay. Results revealed that Qside. Cof, Rsd RQ are dominant factors and should be treated as a major design concern. Among all the parameters, Lsd Tg and Ndop are essentially important in parasitic design optimization. By selectively modifying these parameters, parasitic effect is evidently reduced.
In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic pr...
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ISBN:
(纸本)9781424457977
In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic properties, source/drain series resistance (RSD), and driving current. The SDE-RDF induced variations of threshold voltage (Vth) and DIBL in SNWTs with different diameters are found to be modest and decrease as the diameters down-scale. However, SDE-RDF induced RSd variation in SNWTs is enhanced by abnormal DDA effects, which aggravates the drive current variations with the downscaling of SNWT diameter. The results also show that Vth is the dominant factor in ON/OFF current ratio variation while RSd dominates that of ON current. The tradeoff between RSd and Vth dominant current variations is discussed to give some guidelines for SDE-RDF-aware design in SNWTs.
Voltage pulse dependent resistive switching behavior during SET process in HfO2-based RRAM device is investigated. When a resistor is connected in series to RRAM during the SET process, the resistance uniformity can b...
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Voltage pulse dependent resistive switching behavior during SET process in HfO2-based RRAM device is investigated. When a resistor is connected in series to RRAM during the SET process, the resistance uniformity can be improved. Voltage pulse controlled resistance states were observed. This behavior may provide the new application with the new function circuits.
We calculate valence band structures and transport property of HfO 2 gate dielectric surrounded Ge (110) nanowire with a radial force at the boundary of the insulator. The radial force pushes the valence subbands dow...
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ISBN:
(纸本)9781424435432;9781424435449
We calculate valence band structures and transport property of HfO 2 gate dielectric surrounded Ge (110) nanowire with a radial force at the boundary of the insulator. The radial force pushes the valence subbands downwards. Most of hole effective masses of top five subbands decrease and densities of states' peaks move down as the force increases. The hole mobility in Ge (110) NW significantly increases with higher force values.
In summary, a novel RRAM with the structure of Cu/Si x O y N z /W was first fabricated and its characteristics are thoroughly investigated. The new device exhibited low switching voltages and low reset currents, demon...
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In summary, a novel RRAM with the structure of Cu/Si x O y N z /W was first fabricated and its characteristics are thoroughly investigated. The new device exhibited low switching voltages and low reset currents, demonstrating its potential for low-power applications. Repeatable unipolar resistive switching characteristics in terms of high off/on resistance ratio and good retention capability were observed. The switching mechanism of the device was analyzed and can be explained by the formation and rupture of vacancy filaments.
This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter (ADC) A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only...
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This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter (ADC) A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm^2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.
This paper presents a novel mixed-voltage I/O buffer without an extra dual-oxide CMOS *** mixed-voltage I/O buffer with a simplified circuit scheme can overcome the problems of leakage current and gateoxide reliabilit...
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This paper presents a novel mixed-voltage I/O buffer without an extra dual-oxide CMOS *** mixed-voltage I/O buffer with a simplified circuit scheme can overcome the problems of leakage current and gateoxide reliability that the conventional CMOS I/O buffer *** design is realized in a 0.13-μm CMOS process and the simulation results show a good performance increased by ~34% with respect to the product of power consumption and speed.
A novel voltage controlled oscillator (VCO) sub-band selection circuit to achieve fast phase locked loop (PLL) calibration is presented, which reduces the calibration time by measuring the period difference direct...
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A novel voltage controlled oscillator (VCO) sub-band selection circuit to achieve fast phase locked loop (PLL) calibration is presented, which reduces the calibration time by measuring the period difference directly and accomplishing an efficient search for an optimum VCO sub-band. The sub-band selection circuit was implemented in a 0.18 μm CMOS logic process with a PLL using an 8 sub-band VCO. The measured calibration time is less than 3 μs in a VCO frequency range from 600 MHz to 2 GHz. The proposed circuit consumes 0.64 mA at most.
In this paper, we investigate the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) on deep sub-micron pMOSFETs. It is found that the high temperature of the NBT stress ind...
In this paper, we investigate the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) on deep sub-micron pMOSFETs. It is found that the high temperature of the NBT stress induces an annealing effect by removing part of the radiation-induced positive charges. If we choose a relatively low temperature to avoid the annealing effect, a remarkable radiation acceleration effect on device degradation is observed and the lifetime of pMOSFETs significantly reduces due to more radiation-induced new hole traps in the oxide. However, the acceleration effect seems independent of the oxide electric field during NBT stress. The work in this paper indicates that it is important to choose proper NBT stress conditions if we use NBTI to predict the lifetime of the pMOSFETs which operate in the radiation environments.
A readout integrated circuit for high energy particle detectors is presented. The circuit designed is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper with four selectable peaking time, and an output sta...
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