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Dynamic Resource Allocation Based on User experience in Virtualized Servers

Procedia Engineering 2011年 15卷 3780-3784页

作者： Wei Zhang Jiajun Liu Ying Song Mingfa Zhu Limin Xiao Yuzhong Sun Li Ruan State Key Laboratory of Software Development Environment Beijing 100191 China School of Computer Science and Engineering Beihang University Beijing 100191 China Key Laboratory of Computer System and Architecture Chinese Academy of SciencesBeijing Institute of Computing Technology Chinese Academy of Sciences Beijing China

Web workloads are known to vary dynamically with time which poses a challenge to resource allocation among the applications. In this paper, we argue that the existing dynamic resource allocation based on resource utilization has some drawbacks in virtualized servers. Dynamic resource allocation directly based on real-time user experience is more reasonable and also has practical significance. To address the problem, we propose a system architecture that combines real time measurements and analysis of user experience for resource allocation. We evaluate our proposal using Webbench. The experiment results show that these techniques can judiciously allocate system resources.

关键词： resource allocation virtualized servers user experience

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An ultra-fast hybrid simulation framework for ASIP

An ultra-fast hybrid simulation framework for ASIP

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IEEE International Conference on Electronics, Circuits and systems (ICECS)

作者： Ji Qiu Xiang Gao Yifei Jiang Xu Xiao Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences (CAS) Beijing China Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign Urbana IL USA

ISS (Instruction Set Simulator) plays an important role in pre-silicon software development for ASIP. However, the speed of traditional simulation is too slow to effectively support full-scale software development. In this paper, we propose a hybrid simulation framework which further improves the previous simulation methods by aggressively utilizing the host machine resources. The utilization is achieved by categorizing instructions of ASIP application into two types, namely custom and basic instructions, via binary instrumentation. Then in a way of hybrid simulation, only custom instructions are simulated on the ISS and basic instructions are executed fast and natively on the host machine. We implement this framework for an industrial ASIP to validate our approach. Experimental results show that when the implemented ISS, namely GS-Sim, is applied to practical multimedia decoders, an average simulation speed up to 1058.5MIPS can be achieved, which is 34.7 times of the state-of-art dynamic binary translation simulator and is the fastest to the best of our knowledge.

关键词： Instruments Context Programming Decoding Switches Prototypes Context modeling

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Optimizing Web Browser on Many-Core architectures

Optimizing Web Browser on Many-Core Architectures

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IEEE International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Lingjun Fan Weisong Shi Shibin Tang Chenggang Yan Dongrui Fan Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Department of Computer Science Wayne State University Detroit USA

As more and more Web applications emerging on sever end today, the Web browser on client end has become a host of a variety of applications other than just rendering static Web pages. This leads to more and more performance requirements of a Web browser, for which user experience is very important. This situation may become more urgency when on handheld devices. Some efforts like redesign a new Web browser have been made to overcome this problem. In this paper, we address this issue by optimizing the main processes of the Web browser on a state-of-the-art 64-core architecture, Godson-T, which was developed at Chinese Academy of Sciences, as multi-/many-core architecture to be the mainstream processor in the upcoming years. We start a new core to process a new tab when facing up to intensive URL requests, and we use scratch-pad memory (SPM) of each core as a local buffer to store the HTML source data to be processed to reduce off-chip memory access and exploit more data locality, otherwise, we use DTA to transfer HTML data for backup. Experiments conducted on the cycle-accurate simulator show that, starting each tab process by a new core could obtain 5.7% to 50% speedup with different number of cores used to process corresponding URL requests, with on-chip scratchpad memory of each core used to store the HTML data, more speedup could be achieved when number of cores increase. Also, as Data Transfer Agent (DTA) used to transfer the HTML data, the backup of HTML data can get 2X to 5X speedups according to different data amount.

关键词： Browsers HTML Web pages Layout Multicore processing system-on-a-chip

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Dynamic register promotion of stack variables 11

Dynamic register promotion of stack variables

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International Symposium on Code Generation and Optimization (CGO)

作者： Jianjun Li Chenggang Wu Wei-Chung Hsu Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Deparunent of Computer Science National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)9781612843568

Dynamic Binary Translation (DBT) has been widely used in various applications. Although new architectures and micro-architectures often create performance opportunities for programmers and compilers, such performance opportunities may not be exploited by legacy executables. For example, the additional general-purpose and XMM registers in the Intel64 architecture do not benefit the IA-32 binaries. In this paper, we designed and developed a DBT system to dynamically promote stack variables in the source binaries to the additional registers of the target architecture. One of the most challenging problems is how to deal with the possible but rare memory aliases between promoted stack variables and other implicit memory references. We devised a runtime alias detection approach based on the page protection mechanism in Linux and a novel stack switching method to catch memory aliases at run-time. This approach is much less expensive than traditional approaches like inserting address checking instructions. On an Intel64 platform, our DBT system with speculative stack variable promotion has sped up several SPEC CPU2006 benchmarks in IA-32 code, with the largest performance gain over 45%.

关键词： Registers Optimization Switches computer architecture Benchmark testing Runtime Program processors

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A cost-effective substantial-impact-filter based method to tolerate voltage emergencies

A cost-effective substantial-impact-filter based method to t...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Songjun Pan Yu Hu Xing Hu Xiaowei Li Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

Supply voltage fluctuation caused by inductive noises has become a critical problem in microprocessor design. A voltage emergency occurs when supply voltage variation exceeds the acceptable voltage margin, jeopardizing the microprocessor reliability. Existing techniques assume all voltage emergencies would definitely lead to incorrect program execution and prudently activate rollbacks or flushes to recover, and consequently incur high performance overhead. We observe that not all voltage emergencies result in external visible errors, which can be exploited to avoid unnecessary protection. In this paper, we propose a substantial-impact-filter based method to tolerate voltage emergencies, including three key techniques: 1) Analyze the architecture-level masking of voltage emergencies during program execution; 2) Propose a metric intermittent vulnerability factor for intermittent timing faults (IV F itf ) to quantitatively estimate the vulnerability of microprocessor structures (load/store queue and register file) to voltage emergencies; 3) Propose a substantial-impact-filter based method to handle voltage emergencies. Experimental results demonstrate our approach gains back nearly 57% of the performance loss compared with the once-occur-then-rollback approach.

关键词： Microprocessors Delay computer architecture Computational modeling Sensors Benchmark testing

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Trainbow: a new trusted virtual machine based platform

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中国高等学校学术文摘·计算机科学 2010年第1期4卷 47-64页

作者： Yuzhong SUN Yongbing HUANG Yunwei GAO Haifeng FANG Ying SONG Lei DU Kai ZHANG Hongyong ZANG Yaqiong LI Yajun YANG Ran AO Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of SciencesBeijing 100190China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of SciencesBeijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of SciencesBeijing 100190China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of SciencesBeijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of SciencesBeijing 100190China Department of Computer Science and Technology Xi'an Jiaotong University Xi'an 710049China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China

Currently, with the evolution of virtualization technology, cloud computing mode has become more and more popular. However, people still concern the issues of the runtime integrity and data security of cloud computing platform, as well as the service efficiency on such computing platform. At the same time, according to our knowledge, the design theory of the trusted virtual computing environment and its core system software for such network-based computing platform is at the exploratory stage. In this paper, we believe that efficiency and isolation are the two key proprieties of the trusted virtual computing environment. To guarantee these two proprieties, based on the design principle of splitting, customizing, reconstructing, and isolation-based enhancing to the platform, we introduce TRainbow, a novel trusted virtual computing platform developing by our research *** the two creative mechanisms, that is, capacity flowing amongst VMs and VM-based kernel reconstructing, TRainbow provides great improvements (up to 42%) in service performance and isolated reliable computing environment for Internet-oriented, large-scale, concurrent services.

关键词： Computing platform virtual machine capacity service computing trust chain isolation

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Landing Stencil Code on Godson-T

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Journal of computer Science & Technology 2010年第4期25卷 886-894页

作者：崔慧敏王蕾范东睿冯晓兵 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences

The advent of multi-core/many-core chip technology offers both an extraordinary opportunity and a profound challenge. In particular, computer architects and system software designers are faced with a unique opportunity to introducing new architecture features as well as adequate compiler technology -- together they may have profound impact. This paper presents a case study （using the 1-D Jacobi computation） of compiler-amendable performance optimization techniques on a many-core architecture Godson-T. Godson-T architecture has several unique features that are chosen for this study： 1） chip-level global addressable memory in particular the scratchpad memories （SPM） local to the processing cores; 2） fine-grain memory based synchronization （e.g., full-empty bit for fine-grain synchronization）. Leveraging state-of-the-art performance optimization methods for 1-D stencil parallelization （e.g., timed tiling and variants）, we developed and implement a number of many-core-based optimization for Godson-T. Our experimental study shows good performance in both execution time speedup and scalability, validate the value of globally accessed SPM and fine-grain synchronization mechanism （full-empty bits） under the Godson-T, and provides some useful guidelines for future compiler technology of many-core chip architectures.

关键词： many-core, stencil, Jacobi, compiler SPM, fine-grain synchronization

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Beyond Green: Evolution to Adaptability and Recyclability

Beyond Green: Evolution to Adaptability and Recyclability

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IEEE/ACM Int'l Conference on & Int'l Conference on Cyber, Physical and Social Computing (CPSCom) Green Computing and Communications (GreenCom)

作者： Yuzhong Sun Ying Song Key Laboratory of Computer System and Architecture Chinese Academy of Sciences (CAS) Beijing China Institute of Computing Technology Chinese Academy of Sciences (CAS) Beijing China Key Lab. of Comput. Syst. & Archit. Beijing China

In current social computing system, not only hardware but also software experiences a directly discarded mode. Such directly discarded mode may result in huge waste. The major challenge in green computing is the recyclability of the computing system. In order to address this challenge in the software field, this paper proposes a design idea of green software embodying the adaptability and recyclability. The adaptable and recyclable strategy may consist of two phases. The first one is compressing the increasingly deeper software stack, another one is keeping the functionality recycling and code reuse. The adaptability and recyclability mean automatically decomposing the complex software into several parts which are ease to be reused and automatically selecting the feasible parts for the on-writing software. And we also explore the system software design path to adaptability and recyclability in our previous work as well as in the future.

关键词： Hardware Green products Recycling Software design computers Complexity theory

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Optimizing MPI Alltoall Communication of Large Messages in Multicore Clusters

Optimizing MPI Alltoall Communication of Large Messages in M...

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IEEE International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Qiang Li Zhigang Huo Ninghui Sun Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing CN

MPI All to all communication is widely used in many high performance computing (HPC) applications. In All to all communication, each process sends a distinct message to all other participating processes. In multicore clusters, processes within a node simultaneously contend for the same network resource of the node in All to all communication. However, many small synchronization messages are required in All to all communication of large messages. With the contention, their latency is orders of magnitude larger than that without contention. As a result, the synchronization overhead is significantly increased and accounts for a large proportion to the whole latency of All to all communication. In this paper, we analyse the considerable overhead of synchronization messages. Base on the analysis, an optimization is presented to reduce the number of synchronization messages from 3N to 2¡ÌN. Evaluations on a 240-core cluster show that the performance is improved by almost constant ratio, which is mainly determined by message size and independent of system scale. The performance of All to all communication is improved by 25% for 32K and 64K bytes messages. For FFT application, performance is improved by 20%.

关键词： Synchronization Protocols Multicore processing Receivers Bandwidth Program processors Benchmark testing

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Physical Implementation of the 1GHz Godson-3 Quad-Core Microprocessor

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Journal of computer Science & Technology 2010年第2期25卷 192-199页

作者：范宝峡杨梁王江嵋王茹肖斌徐英刘动赵继业 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences Loongson Technology Corporation Limited

The Godson-3A microprocessor is a quad-core version of the scalable Godson-3 multi-core series. It is physically implemented based on the 65 nm CMOS process. This 174 mm2 chip consists of 425 million transistors. The maximum frequency is 1GHz with a maximum power consumption of 15 W. The main challenges of Godson-3A physical implementation include very large scale, high frequency requirement, sub-micron technology effects and aggressive time schedule. This paper describes the design methodology of the physical implementation of Godson-3A, with particular emphasis on design methods for high frequency, clock tree design, power management, and on-chip variation （OCV） issue.

关键词： physical implementation design methodology on-chip variation （OCV） low power clock tree

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