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Physical Implementation of the 1GHz Godson-3 Quad-Core Microprocessor

Journal of computer Science & Technology 2010年第2期25卷 192-199页

作者：范宝峡杨梁王江嵋王茹肖斌徐英刘动赵继业 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences Loongson Technology Corporation Limited

The Godson-3A microprocessor is a quad-core version of the scalable Godson-3 multi-core series. It is physically implemented based on the 65 nm CMOS process. This 174 mm2 chip consists of 425 million transistors. The maximum frequency is 1GHz with a maximum power consumption of 15 W. The main challenges of Godson-3A physical implementation include very large scale, high frequency requirement, sub-micron technology effects and aggressive time schedule. This paper describes the design methodology of the physical implementation of Godson-3A, with particular emphasis on design methods for high frequency, clock tree design, power management, and on-chip variation （OCV） issue.

关键词： physical implementation design methodology on-chip variation （OCV） low power clock tree

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Design and implementation of communication system of the Dawning 6000 supercomputer

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中国计算机科学前沿 2010年第4期4卷 466-474页

作者： Qiang LI Bo LI Zhigang HUO Ninghui SUN National Research Center for Intelligent Computing Systems Beijing 100190China Key Laboratory of Computer System and Architecture Chinese Academy of SciencesBeijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China National Research Center for Intelligent Computing Systems Beijing 100190China Key Laboratory of Computer System and Architecture Chinese Academy of SciencesBeijing 100190China

An increasing number of supercomputers adopt a heterogeneous architecture, consisting of both general purpose CPUs and specialized accelerators. Such design is beneficial for scalability and power, but on the other hand, heterogeneity brings new challenges in communication systems to connect heterogeneous components and provide support for programming. The communication system of the Dawning 6000 connectstwo kinds of heterogeneous processors, Loongson and AMD, and adopts a three layer architecture with an intranode layer between heterogeneous components. To efficiently connect heterogeneous components, the system forms a global address space and provides a mechanism for message transmission via an in-node global store; and employing Infiniband network, provides an OS-bypassing virtualization method to share an Infiniband card between nodes. To facilitate programming on heterogeneous processors, it supports unified parallel C (UPC), with a modified complier based on global address space. Also, aspecial collective network is implemented for collective operations. Results obtained from a prototype system prove these features to be both feasible and efficient.

关键词： hyper parallel processing (HPP) global address space (GAS) virtualization Dawning 6000 unified parallel C (UPC)

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Study on blocked LU decomposition on many-core architecture

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Gaojishu Tongxin/Chinese High Technology Letters 2011年第3期21卷 248-253页

作者： Yu, Lei Liu, Zhiyong Ma, Yike Song, Fenglong Xu, Weizhi Ye, Xiaochun Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100039 China

The authors studied the scientific application LU decomposition deeply. A speedup model for LU decomposition was proposed, and an algorithm for LU decomposition based on bit reverse xor (BRX) was implemented. Then a dynamic absolute balance policy (DABP) algorithm was presented. In order to estimate the algorithms of 2 dimensional (2D) scatter, BRX and DABP, two different estimation functions were given and they were used to estimate the load balance problem of the algorithms. These two functions verify that the DABP algorithm has the best load balance. The simulations of the three algorithms were performed on the many-core architecture Godson-T. The experiments prove that the speedup of the DABP algorithm is 46 and it is the best performance of the three algorithms.

关键词： computer architecture

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Using index in the MapReduce framework

Using index in the MapReduce framework

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12th International Asia Pacific Web Conference, APWeb 2010

作者： An, Mingyuan Wang, Yang Wang, Weiping Key Laboratory of Computer System and Architecture Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Beijing China

ISBN: (纸本)9780769540122

MapReduce is a programming framework introduced by Google for large-scale data processing. It is usually used in a scan-centric fashion where all the data are split into blocks and Maps are generated for each block to scan and process the data in the block, then Reduces merge outputs from all the Maps. When a query intends to process only a subset of the data selected by a predicate, this brute-force method may cause extra I/O overhead spent on irrelevant data, and the overhead for initiating so many Maps may be nontrivial given that the actually interesting data for the query is comparatively small in volume. We propose an approach to integrate the index into the MapReduce execution in which only an appropriate number of Maps are generated, each of which accesses the data using an index. This approach incurs random I/O and remote access to data, so the overall performance depends on both system parameters and the query characteristics. We build a cost model for both this index access execution and the traditional full scan execution. This cost model can be used to choose between the two execution modes before executing a query. Experiments show that the index access execution can greatly outperform full scan execution when the selectivity of the predicate is low, and the cost model predicts the actual execution cost very well so can be used to determine the execution plan for a query. © 2010 IEEE.

关键词： MapReduce

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Integrating DBMSs as a read-only execution layer into Hadoop

Integrating DBMSs as a read-only execution layer into Hadoop

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11th International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2010

作者： An, Mingyuan Wang, Yang Wang, Weiping Sun, Ninghui Key Laboratory of Computer System and Architecture Graduate University of Chinese Academy of Sciences Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769542874

To obtain the efficiency of DBMS, HadoopDB combines Hadoop and DBMS, and claims the superiority over Hadoop in terms of performance. However, the approach of HadoopDB is simply putting MapReduce onto unmodified single-machined DBMSs which has several obvious weaknesses. In essence, HadoopDB is a parallel DBMS with fault tolerance, which incurs unnecessary overhead due to the DBMS legacy. Instead of augmenting DBMS with Hadoop techniques, we propose a new system architecture integrating modified DBMS engines as a read-only execution layer into Hadoop, where DBMS plays a role of providing efficient readonly operators rather than managing the data. Besides the obtained efficiency from DBMS engine, there are other advantages. The modified DBMS engine is able to directly process data from the HDFS (Hadoop Distributed File system) files at the block level, which means that the data replication can be handled by HDFS naturally, and the blocklevel parallelism is easily achieved. The global index access mechanism is added according to the MapReduce paradigm. The data loading speed is also guaranteed by directly writing the data into HDFS with simplified logic. Experiments show that our system outperforms both original Hadoop and HadoopDB styled system. © 2010 IEEE.

关键词： Database systems

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GenerOS: An asymmetric operating system kernel for multi-core systems

GenerOS: An asymmetric operating system kernel for multi-cor...

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24th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2010

作者： Yuan, Qingbo Zhao, Jianbo Chen, Mingyu Sun, Ninghui Key Laboratory of Computer System and Architecture Institute of Compute Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424464432

Due to complex abstractions implemented over shared data structures protected by locks, conventional symmetric multithreaded operating system kernel such as Linux is hard to achieve high scalability on the emerging multi-core architectures, which integrate more and more cores on a single die. This paper presents GenerOS - a general asymmetric operating system kernel for multi-core systems. In principal, GenerOS partitions processing cores into application core, kernel core and interrupt core, each of which is dedicated to a specified function. In implementation, we conduct a delicate modification to Linux kernel and provide the same interface as Linux kernel so that GenerOS is compatible with legacy applications. The better performance of GenerOS mainly benefits from: (1) Applications run on their own cores with minimal interrupt and kernel support;(2) Every kernel service is encapsulated into a serial process so that there will be fewer contentions than conventional symmetric kernel;(3) A slim schedule policy is used in the kernel core to support schedule between system calls with low overhead. Experiments with two typical workloads on 16-core AMD machine show that GenerOS behaves better than original Linux kernel when there are more processing cores (19.6% for TPCH using oracle database management system and 42.8% for httperf using apache web server). © 2010 IEEE.

关键词： Linux

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The optimization of parallel Smith-Waterman sequence alignment using on-chip memory of GPGPU

The optimization of parallel Smith-Waterman sequence alignme...

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2010 IEEE 5th International Conference on Bio-Inspired Computing: Theories and Applications, BIC-TA 2010

作者： Zhang, Qian An, Hong Liu, Gu Han, Wenting Yao, Ping Xu, Mu Li, Xiaoqiang Department of Computer Science and Technology University of Science and Technology of China Hefei China Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424464388

Memory optimization is an important strategy to gain high performance for sequence alignment implemented by CUDA on GPGPU. Smith-Waterman (SW) algorithm is the most sensitive algorithm widely used for local sequence alignment but very time consuming. Although several parallel methods have been used in some studies and shown good performances, advantages of GPGPU memory hierarchy are still not fully exploited. This paper presents a new parallel method on GPGPU using on-chip memory more efficiently to optimize parallel Smith-Waterman sequence alignment presented by Gregory M. Striemer. To minimize the cost of data transfers, on-chip shared memory is used to store intermediate results. Constant memory is also used effectively in our implementation of parallel Smith-Waterman algorithm. Using these two kinds of on-chip memory decreases long latency memory access operations, and reduces demand for global memory when aligning longer sequences. The experimental results show 1.66× to 3.16× speedup over Gregory's parallel SW on GPGPU in terms of execution time and 19.70× speedup on average and 22.43× speedup peak performance over serial SW in terms of clock cycles on our computer platform. © 2010 IEEE.

关键词： Data transfer

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Metadata in digital video repositories: An analysis on author-generated metadata

Metadata in digital video repositories: An analysis on autho...

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2010 International Conference on Information Society, i-Society 2010

作者： Dantas, Joana Socrates Silveira, Regina Melo Ruggiero, Wilson Vicente LARC-Laboratory of Computer Architecture and Networks Department of Computer and Digital System Engineering Escola Politécnica da Universidade São Paulo Brazil

ISBN: (纸本)9780956426338

The growth of digital content generation and its access by the general public have, for the past few years, promoted the importance of resources' metadata, and enhanced the debate on their generation and quality. The improvement of new technologies and users needs have led to new metadata generation practices, which include the author-generated metadata. By studying the current literature on the subject we analyzed the author-generated metadata quality used on a given IPTV service. From the results of this study we propose an alternative methodology for insertion of metadata by the service user, where an auto-complete engine is applied aiming to enhance the system's metadata quality. © 2010 i-Society.

关键词： Metadata

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Extended selective encoding of scan slices for reducing test data and test power

Extended selective encoding of scan slices for reducing test...

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作者： Liu, Jun Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Graduate University of Chinese Academy of Sciences China School of Computer and Information Hefei University of Technology China

Test data volume and test power are two major concerns when testing modern large circuits. Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying a single bit index and copying group data. In this paper, we propose an extended selective encoding which presents two new techniques to optimize this method: a flexible grouping strategy, X bits exploitation and filling strategy. Flexible grouping strategy can decrease the number of groups which need to be encoded and improve test data compression ratio. X bits exploitation and filling strategy can exploit a large number of don't care bits to reduce testing power with no compression ratio loss. Experimental results show that the proposed technique needs less test data storage volume and reduces average weighted switching activity by 25.6% and peak weighted switching activity by 9.68% during scan shift compared to selective encoding. Copyright © 2010 The Institute of Electronics, Information and Communication Engineers.

关键词： Filling

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P-GAS: Parallelizing a cycle-accurate event-driven many-core processor simulator using parallel discrete event simulation 10

P-GAS: Parallelizing a cycle-accurate event-driven many-core...

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24th Annual Workshop on Principles of Advanced and Distributed Simulation, PADS 2010

作者： Lv, Huiwei Cheng, Yuan Bai, Lu Chen, Mingyu Fan, Dongrui Sun, Ninghui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate School Chinese Academy of Sciences China

ISBN: (纸本)9781424472918

Multi-core processors are commonly available now, but most traditional computer architectural simulators still use single-thread execution. In this paper we use parallel discrete event simulation (PDES) to speedup a cycle-accurate event-driven many-core processor simulator. Evaluation against the sequential version shows that the parallelized one achieves an average speedup of 10.9× (up to 13.6×) running SPLASH-2 kernel on a 16-core host machine, with cycle counter differences of less than 0.1%. Moreover, super-linear speedups are achieved between running 1 thread and 8 threads due to reduced overhead of insert-event-to-queue time and increased cache size in parallel processing. We conclude that PDES could be an attractive option for achieving fast cycle-accurate many-core processor simulations. © 2010 IEEE.

关键词： Simulators

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