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International Electron Devices Meeting (IEDM)

作者： A. Elsherbini K. Jun S. Liff T. Talukdar J. Bielefeld W. Li R. Vreeland H. Niazi B. Rawlings T. Ajayi N. Tsunoda T. Hoff C. Woods G. Pasdast S. Tiagaraj E. Kabir Y. Shi W. Brezinski R. Jordan J. Ng X. Brun B. Krisnatreya P. Liu B. Zhang Z. Qian M. Goel J. Swan G. Yin C. Pelto J. Torres P. Fischer Components Research Logic Technology Development Assembly and Test Technology Development Design Engineering Group Corporate Quality Network Global Sourcing for Equipment and Materials Design Enabling Group Intel Corporation USA

ISBN: (纸本)9781665489607

This paper discusses a new generation of heterogeneous integration architectures which we refer to as quasi-monolithic chips (QMC). QMC enables flexible out-of-order combinations of silicon process & packaging techniques to create flexible and ultra-high interconnect density 3D architectures to fit future computing & AI needs. We show the main structural elements of the architecture and its performance including up to 10X interconnect power reduction and density improvements. We also cover the main new process modules needed to enable QMC including high density back-end compatible hybrid bonding and ultra-thick oxide fill modules.

关键词： Three-dimensional displays Optical imaging Silicon Hybrid power systems Dielectrics Optical films Bonding

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A Physical Unclonable Function Leveraging Hot Carrier Injection Aging

A Physical Unclonable Function Leveraging Hot Carrier Inject...

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Annual International Symposium on Reliability Physics

作者： Rachael J. Parker Jyothi Bhaskarr A. Velamala Kuan-Yueh James Shen David Johnston Yao-Feng Chang Stephen M. Ramey Siang-Jhih Sean Wu Padma Penmatsa Design Engineering Group Intel Corporation Hillsboro OR U.S.A Logic Technology Development Quality & Reliability Intel Corporation Hillsboro OR U.S.A Manufacturing and Product Engineering Intel Corporation Folsom CA U.S.A

Physical Unclonable Functions (PUFs) are low-cost cryptographic primitives used to generate unique, secure, and stable IDs for device authentication and secure communication. PUFs rely on process variation inherent in the manufacturing flow making it impossible to predict or clone chip IDs providing a high level of security and tamper resistance. A commonly studied PUF is the memory PUF which suffers high Bit Error Rate (BER) across environmental conditions. This paper introduces a novel NFET PUF featuring a Hot Carrier Injection (HCI) stress mechanism to lower BER to near zero. Post-Si data from a lkb PUF array fabricated in Intel4 FinFET technology is presented in comparison to a hybrid-SRAM style PUF. BER results were studied with different stress parameters enabling manufacturing flow for HCI based PUFs.

关键词： Human computer interaction Bit error rate Hot carrier injection Physical unclonable function FinFETs Silicon Manufacturing

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Material Modeling in Semiconductor Process Applications

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Journal of Microelectronic Manufacturing 2020年第4期3卷 40-50页

作者： Boris A.Voinov Patrick H.Keys Stephen M.Cea Ananth P.Kaushik Mark A.Stettler Logic Technology Development Intel CorporationHillsboro ORUSA95124 Nonvolatile Memory Solutions Group Intel CorporationSanta ClaraCaliforniaUSA95054 Logic Technology Development Intel CorporationNizhniy NovgorodRussian Federation603024

During the past decade,significant progress has been achieved in the application of material modeling to aid technology development in semiconductor manufacturing companies such as *** this paper,we review examples of applications involving a complex set of material modeling tools and methodologies and share our perspective of the future of the *** are given illustrating the landscape of useful physical models and approaches along with commentary addressing tool relevance and simulation efficiency *** the scope of this paper precludes providing in-depth details,references to more focused publications are ***,we outline how to approach constructing a general infrastructure for supporting TCAD material modeling applications.

关键词： TCAD atomistic modeling density functional theory molecular dynamics kinetic Monte Carlo.

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Advanced Node DTCO in the EUV Era

Advanced Node DTCO in the EUV Era

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International Electron Devices Meeting (IEDM)

作者： A. Wei C. Wallace M. Phillips J. Knudsen S. Chakravarty M. Shamanna R. Brain Logic Technology Development Intel Corp Hillsboro OR USA Design Enablement Intel Corp Hillsboro OR USA Design Engineering Group Intel Corp Austin TX USA

ISBN: (数字)9781728188881

ISBN: (纸本)9781728188898

EUV lithography has finally made it into high-volume manufacturing and this has reset the approach to leading-edge Design technology Co-Optimization. ArF immersion lithography multi-pass patterning was on course to push the technology design rules to be so restrictive, that design optimization would become a clear second priority. EUV lithography restores the balance between design optimization for performance, power, and area scale, along with technology optimization for yield and cost. However, due to the late introduction of EUV, this balance may be short-lived, and further rapid improvement in EUV lithography capability is highly anticipated.

关键词： Performance evaluation Extreme ultraviolet lithography Electron devices Optimization Design optimization

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Reliability Characterization for 12 V Application Using the 22FFL FinFET technology

Reliability Characterization for 12 V Application Using the ...

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Annual International Symposium on Reliability Physics

作者： C.-Y. Su M. Armstrong S. Chugh M. El-tanani H. Greve H. Li M. Maksud B. Orr C. Perini J. Palmer L. Paulson S. Ramey J. Waldemer Y. Yang D. Young Logic Technology Development Quality and Reliability Intel Corp. Hillsboro Oregon U.S.A. Portland Technology Development Department Intel Corp. Hillsboro Oregon U.S.A. Device Development Group Intel Corp. Hillsboro Oregon U.S.A.

ISBN: (数字)9781728131993

ISBN: (纸本)9781728132006

The 22FFL technology developed for operation to 3.3V is used to investigate process and design considerations required to extend technology capability to 12 V applications. A prototype chip was carefully designed in close consideration with the technology reliability requirements of the lower voltage components to demonstrate product-level reliability capabilities. The reliability of components such as transistors, well junctions, back-end dielectrics and MIMCAPs is thoroughly characterized and proven robust throughout a 10-year lifetime. The results demonstrate a reliable technology capability that is compliant with industrial standards to enable high-voltage design requirements.

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A Method to Detect Bit Flips in a Soft-Error Resilient TCAM

A Method to Detect Bit Flips in a Soft-Error Resilient TCAM

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作者： Syafalni, Infall Sasao, Tsutomu Wen, Xiaoqing ASIC Development Group Logic Research Company Ltd. Fukuoka814-0001 Japan Department of Computer Science Meiji University Kawasaki214-8571 Japan Department of Creative Information Kyushu Institute of Technology Iizuka820-8502 Japan

Ternary content addressable memories (TCAMs) are special memories which are widely used in high-speed network applications such as routers, firewalls, and network address translators. In high-reliability network applications such as aerospace and defense systems, soft-error tolerant TCAMs are indispensable to prevent data corruption or faults caused by radiation. This paper shows a novel way in generating keys to cover the correct match. It proposes a novel soft-error tolerant TCAM for multiple-bit-flip errors using partial don't-care keys (X-keys). First, this paper observes the case of single-bit-flip errors by X-TCAM. Second, it extends the X-TCAM to the case of multiple-bit-flip errors called KX-TCAM, where K stands for the maximum number of errors k. KX-TCAM corrects up to k -bit-flip errors and enhances the tolerance of the TCAM against soft errors, where k is the maximum number of bit flips in a word of a TCAM. KX-TCAM consists of a TCAM, a preprocessed don't-care-bit index look-up memory (X look-up), and a backup error checking and correction (ECC)-SRAM. First, KX-TCAM randomly selects a search key. After that, KX-TCAM detects multiple-bit-flip errors by the generated X-keys using the X look-up. If the keys match the different locations, then a soft error is suspected and KX-TCAM refreshes the TCAM words by using the backup ECC-SRAM. Experimental results show that the soft-error tolerance capability of KX-TCAM significantly outperforms existing state-of-the-art schemes. Moreover, the hardware overhead of KX-TCAM is small due to the use of a single TCAM. KX-TCAM can be easily implemented and is useful for fault-tolerant packet classifiers. © 1982-2012 IEEE.

关键词： Static random access storage

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Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process 29

Low-voltage metal-fuse technology featuring a 1.6V-programma...

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29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015

作者： Kulkarni, S.H. Chen, Z. Srinivasan, B. Pedersen, B. Bhattacharya, U. Zhang, K. Advanced Design Logic Technology Development Intel Corporation HillsboroOR United States NVM Solutions Group Intel Corporation HillsboroOR United States Custom Foundry Intel Corporation HillsboroOR United States

ISBN: (纸本)9784863485020

This work introduces the first high-volume manufacturable metal-fuse technology in a 22nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 16.4μm2 1T1R bit cell is presented that delivers a record low program voltage of 1.6V. This low-voltage operability allows the array to be coupled with logic-voltage power delivery circuits. A charge pump voltage doubler operating on a 1V voltage rail is demonstrated in this paper with healthy fusing yield. © 2015 JSAP.

关键词： Metals

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High sigma measurement of random threshold voltage variation in 14nm logic FinFET technology

High sigma measurement of random threshold voltage variation...

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Symposium on VLSI technology

作者： M. D. Giles N. Arkali Radhakrishna D. Becher A. Kornfeld K. Maurice S. Mudanai S. Natarajan P. Newman P. Packan T. Rakshit Design Technology Solutions Intel Corporation Hillsboro OR USA Logic Technology Development Intel Corporation Hillsboro OR USA Device Development Group Intel Corporation Hillsboro OR USA

Random variation of threshold voltage (Vt) in MOSFETs plays a central role in determining the minimum operating voltage of products in a given process technology. Properly characterizing Vt variation requires a large volume of measurements of minimum size devices to understand the high sigma behavior. At the same time, a rapid measurement approach is required to keep the total measurement time practical. Here we describe a new test structure and measurement approach that enables practical characterization of Vt distributions to high sigma and its application to 14nm logic FinFET technology. We show that both NMOS and PMOS single fin devices have very low random Vt variation of 19mV and 24mV respectively, normally distributed out to +/-5σ.

关键词： Threshold voltage FinFETs logic gates Time measurement Periodic structures

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Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process

Low-voltage metal-fuse technology featuring a 1.6V-programma...

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Symposium on VLSI Circuits

作者： S H Kulkarni Z Chen B Srinivasan B Pedersen U Bhattacharya K Zhang Advanced Design Logic Technology Development Intel Corporation Hillsboro OR USA NVM Solutions Group Custom Foundry Intel Corporation Hillsboro OR USA

This work introduces the first high-volume manufacturable metal-fuse technology in a 22nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 16.4μm 2 1T1R bit cell is presented that delivers a record low program voltage of 1.6V. This low-voltage operability allows the array to be coupled with logic-voltage power delivery circuits. A charge pump voltage doubler operating on a 1V voltage rail is demonstrated in this paper with healthy fusing yield.

关键词： Fuses Arrays Charge pumps Programming Microprocessors System-on-chip

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Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process

Low-voltage metal-fuse technology featuring a 1.6V-programma...

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Symposium on VLSI technology

作者： S H Kulkarni Z Chen B Srinivasan B Pedersen U Bhattacharya K Zhang Advanced Design Logic Technology Development Intel Corporation Hillsboro OR USA NVM Solutions Group Intel Corporation Hillsboro OR USA Custom Foundry Intel Corporation Hillsboro OR USA

This work introduces the first high-volume manufacturable metal-fuse technology in a 22nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 16.4μm 2 1T1R bit cell is presented that delivers a record low program voltage of 1.6V. This low-voltage operability allows the array to be coupled with logic-voltage power delivery circuits. A charge pump voltage doubler operating on a 1V voltage rail is demonstrated in this paper with healthy fusing yield.

关键词： Fuses Arrays Charge pumps Programming Microprocessors System-on-chip

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