The activation efficiency of conventionell furnace annealing (650°C-900°=C, 30 min, SiO 2 cap, N 2 ambient) and rapid thermal annealing (600°C-900°C, with and without SiO 2 cap, N 2 ambient) ha...
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The activation efficiency of conventionell furnace annealing (650°C-900°=C, 30 min, SiO 2 cap, N 2 ambient) and rapid thermal annealing (600°C-900°C, with and without SiO 2 cap, N 2 ambient) has been compared in Si doped GaInAs layers grown lattice matched by either OMVPE or LPE on InP. Carrier profiles and atomic profiles have been determined by selective Hall measurement, C/V profiling and SIMS measurements. For an implantation dose of 2*10 14 cm -2 and rapid thermal annealing at 900 °C activation of 69 % with a sheet resistance of 20 Ω is found. Rapid thermal annealing and furnace annealing lead to comparable activation efficiency and Hall mobility data. A broadening of carrier concentration profile for furnace annealing at 700°C, 30 min is observed. Rapid thermal annealing between 700°C and 900°C leads to no measurable change in Si profile. In case of low dose Si implantation in OMVPE grown layers highest activation (65 %) is achieved for rapid thermal annealing at 700°C. The electron mobility at a doping concentration of 10 17 cm -3 is 5800 cm 2 V -1 s -1 . For low dose Si implantation in LPE grown layers the activation is 100% after rapid annealing at 800°C. Long furnace annealing (700°C, 30 min ) results in an anomalous high carrier concentration at the surface.
Reflow of phosphosilicate glass (PSG) using the short‐duration rapid thermal annealing technique at temperatures ranging between 1000° and 1300°C is reported. Excellent control of the reflow has been obtain...
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Reflow of phosphosilicate glass (PSG) using the short‐duration rapid thermal annealing technique at temperatures ranging between 1000° and 1300°C is reported. Excellent control of the reflow has been obtained. Heating times required for reflow decrease rapidly with increased temperature. Addition of to the anneal ambient reduces the lag time to reflow and also induces greater flow. Dopant redistribution in the underlying silicon during PSG reflow was measured. Results correlating the phosphorus mole percent, anneal temperature, and the anneal ambient to the overall reflow characteristics of the PSG are presented.
The effects of rapid thermal processing (RTP) on the electrical properties of thin gate oxides in MOS devices have been studied. MOS capacitors have been analyzed by capacitance-voltage (C-V), current-voltage (I-V), a...
The effects of rapid thermal processing (RTP) on the electrical properties of thin gate oxides in MOS devices have been studied. MOS capacitors have been analyzed by capacitance-voltage (C-V), current-voltage (I-V), and constant current stress techniques. MOSFET degradation due to hot carrier injection has also been investigated. No significant RTP-induced degradation was detected in any category of the device properties considered here. An abnormal trapping behavior was observed on the wafer annealed at 1100°C for 5 seconds.
A novel technique for the fabrication of shallow, silicided p+-n junctions with excellent electrical characteristics has been developed. The technique utilizes the ion implantation of dopants into silicide layers form...
A novel technique for the fabrication of shallow, silicided p+-n junctions with excellent electrical characteristics has been developed. The technique utilizes the ion implantation of dopants into silicide layers formed by ion-beam mixing with Si ions and low temperature annealing, and the subsequent drive-in of implanted dopants into the Si substrates to form shallow junctions. This technique can be easily applied to the fabrication of MOSFETs in a self-aligned fashion, and can have a significant impact on CMOS VLSI technology.
Double-diffused shallow junctions have been formed by ion implantation of both phosphorus and arsenic ions into silicon substrates and rapid thermal annealing. Experimental results on defect removal, impurity activati...
Double-diffused shallow junctions have been formed by ion implantation of both phosphorus and arsenic ions into silicon substrates and rapid thermal annealing. Experimental results on defect removal, impurity activation and redistribution, effects of Si preamorphization, and electrical characteristics of Ti-silicided junctions are presented.
This book discusses the latest developments and outlines future trends in the fields of microelectronics, electromagnetics and telecommunication. It contains original research works presented at the International Conf...
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ISBN:
(数字)9789811685545
ISBN:
(纸本)9789811685538;9789811685569
This book discusses the latest developments and outlines future trends in the fields of microelectronics, electromagnetics and telecommunication. It contains original research works presented at the International Conference on microelectronics, Electromagnetics and Telecommunication (ICMEET 2021), held in Bhubaneswar, Odisha, India during 27–28 August, 2021. The papers were written by scientists, research scholars and practitioners from leading universities, engineering colleges and R&D institutes from all over the world and share the latest breakthroughs in and promising solutions to the most important issues facing today’s society.
This book provides the most recent, quality research papers accepted and presented in the 6th International Conference on Artificial Intelligence and Applied Mathematics in engineering (ICAIAME 2024), held in 26-27-28...
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ISBN:
(数字)9783031925528
ISBN:
(纸本)9783031925511;9783031925542
This book provides the most recent, quality research papers accepted and presented in the 6th International Conference on Artificial Intelligence and Applied Mathematics in engineering (ICAIAME 2024), held in 26-27-28 September 2024 at Warsaw, Poland. Objective of the book is to provide important and innovative research for developments—improvements within different engineering fields, which are highly interested in using artificial intelligence and applied mathematics. As a collection of the outputs from ICAIAME 2024, the book ensures a perspective in terms of especially futuristic solution approaches to advance the society through innovative engineering efforts. The book allows researchers and practitioners from both academia as well as industry to exchange, share their ideas and keep themselves up to date (in terms of knowledge) in the context of the latest research efforts and further opportunities arising. As the proceedings of the ICAIAME 2024, the book eventually plays a remarkable, active role in accumulating the most recent, significant works of artificial intelligence and applied mathematics to shape both the present and future of engineering disciplines.
In the Internet of Things (IoT) era, the pervasive application of tremendous end devices puts forth an unprecedented demand for data processing. To address this challenge, the end-edge-cloud system has emerged as a so...
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In the Internet of Things (IoT) era, the pervasive application of tremendous end devices puts forth an unprecedented demand for data processing. To address this challenge, the end-edge-cloud system has emerged as a solution, where task offloading plays a crucial role in efficiently allocating computing resources. Meanwhile, driven by the growing social awareness of privacy, privacy-aware task offloading methods have attracted significant attention. However, existing privacy-aware task offloading methods face various limitations, such as being applicable to specific scenarios, poor transfer ability of offloading strategies, etc. This paper studies the privacy-aware task offloading problem in the end-edge-cloud system and proposes PATO, a Privacy-Aware Task Offloading strategy. PATO consists of two core modules. Specifically, a novel self-supervised feature mapping module transforms sensitive information via complex unidirectional mapping. Subsequently, a DRL-based decision-making module is trained to utilize transformed information to make task offloading decisions. Subtly combining the self-supervised feature mapping module and the DRL-based decision-making module, the proposed PATO addresses both privacy protection and task offloading challenges. Furthermore, PATO is designed as a general solution for task offloading problems and exhibits good transfer ability.
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