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Symposium on VLSI Technology

作者： R. Annunziata T. Ghilardi M. Tosi Non Volatile Memory Process Dev. STMicroelectronics Agrate Brianza Italy Non Volatile Memory Process Development Central R&D STMicroelectronics Agrate-Brianza Italy

ISBN: (纸本)0780354389

Substrate negative polarization enhances gate current in submicron MOSFETs, improving two different hot carrier mechanisms (Esseni et al., 1998): CHEI (channel hot electron injection) and CISEI (channel induced secondary electron injection) (Bude et al, 1995). This effect is of particular interest in flash memory research, because it allows low power programming. In this paper, we first identify which of the two mechanisms prevails for each bias scheme, with or without body bias. Then, we analyse experimentally the impact of some device parameters and temperature on the total gate current, identifying the different trends of CHEI and CISEI. Finally, the programming disturbs are evaluated. Substrate polarization could worsen the electrical stress of the cells which belong to the same word line or bit line of the selected one, since the substrate is shared by the whole array.

关键词： Temperature Polarization Electrons Doping nonvolatile memory Implants Flash memory MOSFETs Threshold voltage Research and development

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Charge trapping mechanism under dynamic stress and its effect on failure time [gate oxides]

Charge trapping mechanism under dynamic stress and its effec...

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Annual International Symposium on Reliability Physics

作者： G. Ghidini D. Brazzelli C. Clementi F. Pellizzer Non Volatile Memory Process Development Central R&D STMicroelectronics Agrate-Brianza Italy

The aim of this work was to investigate the effect of dynamic versus DC voltage stress applied to thin oxides. A longer lifetime was observed under pulsed stress at high electric fields. When increasing the frequency, we noticed an increment of lifetime and a different trapped charge location, regardless of the stress polarity. To detect the charge trapping evolution under pulsed stress, we used a new experimental procedure. Fast transitory phenomena detected using this technique are interpreted as charging and discharging of positive traps located in the anodic region. The consequent reduction of the effective positive charge allows us to explain the lifetime enhancement and the charge trapping evolution. We also compared the behaviour under pulsed stress of oxides grown in dry or steam environments. The lifetime increase is more relevant in dry oxides showing a correlation between the interface quality and the oxide reliability in dynamic mode.

关键词： Voltage Testing Pulse measurements Dielectric substrates Electric breakdown Frequency Thermal stresses Charge carrier processes Monitoring Capacitors

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An innovative process sequence to obtain reliable nitrided active dielectrics

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JOURNAL OF non-CRYSTALLINE SOLIDS 1997年 216卷 198-201页

作者： Ghidini, G Clementi, C Central R&D Non-Volatile Memory Process Development SGS-Thomson Microelectronics Via C. Olivetti 2 20041 Agrate Brianza Italy

Nitrided active oxides are more and more widely used in semiconductor industry for their attractive qualities in terms of reliability and resistance to the degradation induced by current flow. Depending on the process sequence, it could happen to grow a new active dielectric in an area on which a nitrided oxide was previously grown. Nitrogen pile-up at the Si/SiO2 interface during the nitridation process [Y. Okada et al., J. Electrochem. Sec. 140 (1993) L87;H. Fukuda et al., in: The Physics and Chemistry of SiO2 and the Si/SiO2 interfaces, ed. H.Z. Massoud, E.H. Poindexter and C.R. Helms (Electrochemical Society, Pennington, NJ, 1996) p. 15;D. Bouvet et al., J. Appl. Phys. 79 (1996) 7114] yields a modification of bulk Si surface characteristics, influencing the quality of the oxides grown subsequently to the nitrided oxide removal. In this paper we present an analysis of the oxide quality, reporting their properties as a function of growing techniques (i.e., whether the second oxide is nitrided or not) and of first oxide removal time (i.e., of the overetch that the Si surface experience). Exponentially ramped current stress (ERCS) and constant current stress (CCS) investigation were performed showing that to achieve a good quality of the second dielectric a further nitridation is necessary. The quality itself is strictly connected to the amount of etching of the first nitrided oxide. (C) 1997 Elsevier Science B.V.

关键词： Dielectric materials

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A scalable single poly EEPROM cell for embedded memory applications

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MICROELECTRONICS JOURNAL 1997年第6-7期28卷 657-661页

作者： Baldi, L Cascella, A Vajana, B Non Volatile Memory Process Development SGS-THOMSON Microelectronics Via C. Olivetti 2 I-20041 Agrate Brianza Italy. Tel: -39-39 6035310. Fax:-39-39 6035233

An increasing number of integrated circuits requires the embedding of a limited amount (up to 16-64 kbits) of EEPROM memory. For this application, low process complexity, robust structure and good reliability are more important than small cell size. In this paper we present the design and characterization of a single poly EEPROM cell, optimized for embedded applications, and characterized by a good shrink potential. A cell area of 68.7 mu m(2) has been obtained in 0.7 mu m technology, and electrical characterization has shown the possibility of achieving a programming time of less than 1 msec, while an endurance of more than 10 million cycles has been achieved at 125 degrees C, with a programming time of 2 msec. By further shrink of the same basic layout, cell areas of 55 and 44 mu m(2) have been obtained, and similar programming and endurance performances have been demonstrated. (C) 1997 Elsevier Science Ltd.

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Passivation scheme impact on retention reliability of non volatile memory cells

Passivation scheme impact on retention reliability of non vo...

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IEEE International Workshop Integrated Reliability

作者： R. Bottini A. Cascella F. Pio B. Vajana Non Volatile Memory Process Development Central Research and Development Italy

non volatile memory cells must retain the data (i.e. the charge stored in the floating gate) during the device lifetime, typically at least 10 years. In this work we study the impact of different passivation layers on the data retention of single polysilicon EEPROM cells, processed with an advanced 0.7 /spl mu/m process technology. Three passivation layers have been considered: (1) Phosphorus doped Silicon Glass (PSG), (2) Planarized (Oxynitride/SOG/Oxynitride/PSG), and (3) UV-Nitride. Accelerated tests were performed at high temperature (250-350/spl deg/C) up to 500 hours in order to monitor the threshold voltage shift of the floating gate transistor programmed either in the written or in the erased state. In the case of planarized passivation and of UV-nitride passivation the charge loss is small and it largely fulfils the data retention requirements; in the case of PSG passivation a much higher charge loss is observed. The effect of tunnel oxide degradation after extended cycling (1 Mcycles) has been investigated. No significant difference has been found after 200 hours at 250/spl deg/C between cycled and one time programmed cells, evidencing that the charge loss mechanism does not involve tunnel oxide degradation. The activation energy of the charge loss mechanism has been evaluated in the case of planarized passivation, using written cells. The measured value is 1.84 eV. The impact of different passivation schemes was studied with conventional techniques, the best results were obtained with the planarized passivation stack and with the UV-nitride layer.

关键词： Passivation nonvolatile memory Degradation EPROM Silicon Glass Life estimation Testing Performance evaluation Temperature

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F contamination effects on intrinsic and extrinsic gate oxide reliability

F contamination effects on intrinsic and extrinsic gate oxid...

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IEEE International Workshop Integrated Reliability

作者： G. Ghidini D. Drera F. Maugain Non Volatile Memory Process Development Central R and D-SGS-THOMSON Microelectronics Italy

The subject of this work is the study of the effect of fluorine contaminants on the intrinsic and extrinsic gate oxide reliability. After a brief introduction in which the author explains the known effects of fluorine contaminants on the oxide quality, the the test structures used in this work to separate the effect of fluorine contaminants are described. The author then presents some typical TDDB distributions showing the effects of fluorine contaminants and reports also a study of the TDDB dependence on the tested areas to verify if clustering of defects are present at such high fluorine concentrations. The author explains how he statistically treated the experimental results. He considered bimodal distributions separated in an intrinsic and an extrinsic part, showing in detail the effects of fluorine on the intrinsic and extrinsic failure mode. The author also presents some data on charge trapping to explain the above results and finally draws some conclusions.

关键词： Contamination Atomic measurements Testing Pollution measurement Performance evaluation MOS capacitors Logic gates Temperature Atomic layer deposition Degradation

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