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A 12-μm Pixel Pitch 640 x 512 resolution 120 ^°C Operating range TEC-Less Bolometric Infrared Imager With Ultra Low responsivity drift

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IEEE TrANSACTIONS ON circuits ANd SYSTEMS II-EXPrESS BrIEFS 2024年第3期71卷 1072-1076页

作者： Shi, Xueyou Liu, dahe Yu, Shanzhe Zhang, Yacong Lu, Wengao Chen, Zhongjian Peking Univ Sch Integrated Circuits Natl Key Lab Sci & Technol Micro Nano Fabricat Beijing 100871 Peoples R China Peking Univ Beijing Adv Innovat Ctr Integrated Circuits Beijing 100871 Peoples R China Beijing AK Technol Co Ltd R&D Ctr Beijing 100085 Peoples R China

TEC-less bolometric imagers have the advantages of size, weight, power, and cost (SWaP-C). However, the imagerfs responsivity drifts dramatically with the substrate temperature, resulting in scene dynamic range (dr) degradation. This brief presents a 120(degrees)C operating range TEC-less bolometric imager with ultra-low responsivity drift. The proposed imagerfs low responsivity temperature coefficient is obtained by summing the positive and negative temperature coefficients. In the readout circuit, a poly resistor and a bolometer resistor are used in series as the feedback resistor of the pre-amplifier to accomplish the above summing. The proposed readout circuit is a low-cost improvement and hardly increases the complexity. A 12 mu m pixel pitch 640x512 resolution vanadium oxide (VOx) bolometric imager is implemented for verification. Measurement results show that the responsivity drift is less than 20% within the 120(degrees) temperature range, while the drift is higher than 90% without compensation. The proposed imagerfs measurement noise equivalent temperature difference (NETd) is 45 mK, demonstrating good NETd performance. The proposed imager is suitable for TEC-less wide temperature range low SWaP-C applications.

关键词： Temperature measurement Temperature distribution Bolometers resistors Imaging Substrates resistance TEC-less bolometric imager responsivity drift wide temperature range NETd

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An Integrated Fluorescence Optical Fiber Temperature Sensor Front-End Based on a ring-Gate-Isolated Photodiode

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IEEE SENSOrS JOUrNAL 2024年第8期24卷 12276-12285页

作者： Xiong, Bingjun Yang, Jian Wang, Yang Guan, Jian Yan, Feng Zhang, Qian Choubey, Bhaskar Liu, Jingjing Sun Yat Sen Univ Sch Elect & Commun Engn Shenzhen 518107 Peoples R China Hunan Normal Univ Sch Phys & Elect Changsha 410081 Peoples R China Peking Univ Sch Integrated Circuits Key Lab Microelect Devices & Circuits MoE Beijing 100091 Peoples R China Sun Yat Sen Univ Sch Mat Shenzhen 518107 Peoples R China Siegen Univ Analogue Circuits & Image Sensors D-57076 Siegen Germany

Fluorescence optical fiber temperature sensors have found widespread use in harsh environments with electromagnetic interference, high voltages, flammability, and combustibility due to their excellent insulating properties. However, conventional fluorescence detection systems are constructed from discrete photodiodes and other front-end circuit chips, which cause bulky size, inferior detection efficiency, and degraded signal-to-noise performance. To address these issues, an integrated optical front-end circuit for fluorescence detection was proposed. The front-end circuit monolithically integrated a ring-gate-isolated photodiode (rGI-Pd) device, a transimpedance amplifier (TIA), and a bandgap reference (BGr) circuit. The rGI-Pd enabled the detection of the fluorescence afterglow signals, while the TIA circuit converted the photocurrent generated by the rGI-Pd into a measurable photovoltage output. The rGI-Pd utilized a P-well guard ring structure to prevent edge breakdown by isolating the avalanche region from the shallow trench. The dummy ring-gate created an inverted pyramid hole profile, focusing the electric field on the planar junction to enhance photodetection, which reduced trapping effects and dark counts. The proposed front-end circuit was fabricated using a standard 0.18 mu m bipolar CMOS dMOS (BCd) process. The measurement results demonstrated that the avalanche breakdown voltage (BV) of the rGI-Pd was 13.05 V. The front-end circuit achieved a responsivity of 17.29 A/W at 500 nm wavelength, under a 13.88 V reverse bias voltage applied on the rGI-Pd. Moreover, the front-end's dark voltage measured 0.908 V, with an optimal temperature coefficient (TC) of 41.01 ppm/degree celsius within the temperature range of -40 degree celsius to 85 degree celsius. The proposed front-end circuit was suitable for fluorescence fiber temperature sensing applications.

关键词： Fluorescence Photodiodes Electric fields Temperature sensors Temperature measurement Optical fiber amplifiers Logic gates Optical sensor ring-gate-isolated photodiode (rGI-Pd) transimpedance amplifier (TIA)

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Effects of the VGS sweep range on the short channel effect in negative capacitance FinFETs

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Science China(Information Sciences) 2024年第6期67卷 463-464页

作者： Fan ZHANG Zhaohao ZHANG Jiaxin YAO Qingzhu ZHANG Gaobo XU Zhenhua WU Huan LIU Genquan HAN Yan LIU Huaxiang YIN Integrated Circuit Advanced Process R&D Center State Key Lab of Fabrication Technologies for Integrated CircuitsInstitute of Microelectronics of Chinese Academy of Sciences School of Microelectronics Xidian University School of Integrated Circuits University of Chinese Academy of Sciences

As the CMOS technology scaling is reaching fundamental limits,there is a substantial demand for energy-efficient devices with lower operating *** capacitance field-effect transistors （NCFETs） exhibit the capability to amplify the gate voltage and become promising candidates for future advanced process *** （FE） HfO2-based materials,

关键词： channel sweep range capacitance effects finfets negative short

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A Multiscale Anisotropic Thermal Model of Chiplet Heterogeneous Integration System

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IEEE TrANSACTIONS ON VErY LArGE SCALE INTEGrATION (VLSI) SYSTEMS 2024年第1期32卷 178-189页

作者： Wang, Chenghan Xu, Qinzhi Nie, Chuanjun Cao, He Liu, Jianyun Zhang, daoqing Li, Zhiqiang Chinese Acad Sci Inst Microelect EDA Ctr Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuits Beijing 100049 Peoples R China State Key Lab Fabricat Technol Integrated Circuits Beijing 100029 Peoples R China Beijing Key Lab Three Dimens & Nanometer Circuit D Beijing 100029 Peoples R China

due to a variety of limitations on the system-on-chip (SoC), the microelectronics industry is now facing challenges and making slow progress in recent years. With architecture design and advanced packaging advantages, chiplet heterogeneous integration (CHI) systems have become a promising solution to long-lasting hardship. However, high power consumption in CHI systems generates massive heat and makes thermal design a demanding task. Therefore, an accurate tool for thermal simulation is indispensable in the design flow. In this article, a multiscale anisotropic thermal model is proposed for the CHI systems. It considers the feature-scale thermal conductivities of different materials to predict the package-scale steady-state temperature fields. Specifically, the local material composition and thermal conductivity of redistribution layers (rdLs) are extracted from design layout files by constructing an equivalent thermal conductivity algorithm of local feature structures. As for through silicon via (TSV) and bump arrays, the anisotropic distributions of thermal conductivity can also be derived with equivalent algorithms. Other structures are considered homogeneous blocks to significantly reduce the computational expense without losing the generality of the proposed model. Compared with the previous isotropic thermal model of CHI systems, the present multiscale anisotropic thermal model is proven to make temperature prediction and hotspot detection more reliable. With this tool, the reliability problems that are unpredictable and obscure for isotropic thermal models can be identified in advance, and more reasonable design space can be explored in the design flow of the CHI systems.

关键词： Anisotropic chiplet heterogeneous integration (CHI) equivalent algorithm steady-state thermal conductivity thermal simulation

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Ultra-Sharp Multimode Waveguide Bends Based on Superellipse Curves and Shallowly Etched Nanoslots designed by an Intelligent Algorithm

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JOUrNAL OF LIGHTWAVE TECHNOLOGY 2024年第15期42卷 5249-5261页

作者： dou, Tonghui Yue, Song Hou, Yu Wang, ran Shi, Haiyan Li, Yuhang Feng, Yanming Zhang, Zichen Chinese Acad Sci Inst Microelect Microelect Instruments & Equipment R&D Ctr Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuits Beijing 100049 Peoples R China

As an emerging technique, mode division multiplexing (MdM) can effectively increase the data capacity in communication networks. High-performance multimode waveguide bends with small device footprints play an indispensable role in multimode photonics and MdM technique. Previously reported multimode waveguide bends still face the challenge of limited number of supported modes and relatively large device footprint. To tackle these challenges, based on the intelligent inverse design algorithm that combines adaptive genetic algorithm (AGA) and finite element method (FEM) simulation, a kind of multimode waveguide bend based on superellipse curves and shallowly-etched subwavelength nanoslots is proposed in this work. Numerical simulation results confirm that the multimode waveguide bends can support up to 5 TE modes and 8 TE/TM modes (4 TE + 4 TM), whose bending radius is only 3.55 and 3.25 mu m, respectively. All devices can be characterized as ultra-sharp 90 degrees multimode waveguide bends with low loss and low crosstalk. Moreover, this work reconfirms the good generality of our intelligent design methodology, which can be applied to the design and optimization of various photonic devices. Meanwhile, the proposed multimode waveguide bends hold good prospect in application of MdM techniques in multimode silicon photonics.

关键词： Optical waveguides Crosstalk Bending Claddings Waveguide transitions Shape Optical losses Mode-division multiplexing multimode waveguide bends inverse design genetic algorithm superellipse curve

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An Electrical-Thermal Co-Simulation Model of Chiplet Heterogeneous Integration Systems

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IEEE TrANSACTIONS ON VErY LArGE SCALE INTEGrATION (VLSI) SYSTEMS 2024年第10期32卷 1769-1781页

作者： Ma, Xiaoning Xu, Qinzhi Wang, Chenghan Cao, He Liu, Jianyun Zhang, daoqing Li, Zhiqiang Chinese Acad Sci Inst Microelect Beijing 100045 Peoples R China Chinese Acad Sci Key Lab Fabricat Technol Integrated Circuits Beijing 100045 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuits Beijing 101408 Peoples R China Beijing Key Lab Three Dimens & Nanometer Circuit D Beijing 100029 Peoples R China

Chiplet heterogeneous integration (CHI) is one of the important technology choices to continue Moore's law. However, due to the characteristics of high power and low supply voltage in CHI systems, heavy currents need to flow through the power delivery network (PdN), and the Joule heating effect will result in the overall temperature increase of the CHI system. Meanwhile, the high temperature will cause the current as well as the performance of the system to degrade and a series of reliability problems will occur. In this article, an effective electrical-thermal coupling model is proposed to predict the steady-state temperature distribution of a 2.5-d CHI system considering the Joule heating effect and the temperature effect on the Ir drop. The equivalent electrical conductivity model is also built up to describe the design features of the redistribution layer (rdL), bump, and through silicon via (TSV) structures based on the electrical-thermal duality. Furthermore, the governing equations for voltage distribution and temperature distribution are solved simultaneously by utilizing the finite volume method (FVM) with nonuniform mesh to realize the electrical-thermal co-simulation of the multiscale CHI system. The model application is further performed to investigate the influence of the model parameters on the voltage drop and temperature distribution of the CHI system. The verified systems and simulated results of the present investigation demonstrate the viability and accuracy of voltage and temperature field co-simulation and indicate that the new proposed electrical-thermal model is helpful in thermal and voltage drop analysis of packaging structures with the Joule heating effect and can be adopted to assist in the physical design optimization of 2.5-d CHI or 3-d heterogeneous stacked chips.

关键词： Chiplet heterogeneous integration (CHI) system electrical-thermal co-simulation equivalent electrical conductivity finite volume method (FVM)

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A wearable enzyme sensor enabled by the floating-gate OECT with poly(benzimidazobenzophenanthroline) as the catalytic layer

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JOUrNAL OF NANOBIOTECHNOLOGY 2025年第1期23卷 1-11页

作者： Ji, Jianlong Xiao, Jing Zhang, Fan Wang, Zhaoqun Zhou, Tianyuan Niu, Xiaorong Zhang, Wendong Sang, Shengbo Chai, Xiaojie Yan, Sheng Taiyuan Univ Technol Coll Integrated Circuits Taiyuan Peoples R China 6D Artificial Intelligence Biomed Res Inst Taiyuan Peoples R China Shenzhen Univ Inst Adv Study Shenzhen Peoples R China

With the advantages of miniaturization, simple device structure, and fast response, the organic electrochemical transistor (OECT) has become an emerging platform for developing wearable enzyme sensors for real-time health monitoring. The floating gate (FG) OECT employs a distinct signal acquisition and amplification structure, mitigating the effects of non-specific physical adsorption during the sensing process and preventing contamination of the electrolyte solution by side reaction products. The current work reports a feasible wearable enzyme sensor using a poly(benzimidazobenzophenanthroline) (BBL)-Nafion-enzyme-Nafion stacking structure as the sensing layer of the FG OECT. Based on the experimental results, the BBL film with an area of 3.14 mm2 and a thickness of 175 nm can generate an open circuit potential of 199.61 mV in 10- 1 M hydrogen peroxide compared with the blank control. Then, the FG OECT is integrated with the flexible microfluidic systems for on-skin detection of glucose, lactate, and uric acid with sensitivities of 92.47, 152.15, and 74.27 mu Addle dot>dec- 1, respectively. This FG OECT-based wearable enzyme sensor will open new windows for multiplexed detection of sweat metabolites.

关键词： OECT Microfluidics Wearable Enzyme sensor

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ITP-PAd: A Timing Monitoring Mechanism for AVS Systems Using Intersection Timing Prediction and Path Activation detection

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IEEE TrANSACTIONS ON circuits ANd SYSTEMS II-EXPrESS BrIEFS 2025年第5期72卷 753-757页

作者： Wang, Kangning Zhao, Huidong Li, Zhi Liu, Jiliang Qiao, Shushan Chinese Acad Sci Smart Sensing Chip & Syst R&D Ctr Inst Microelect Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuits Beijing 101408 Peoples R China

In-situ timing monitoring technology is widely used in adaptive voltage scaling (AVS) system to provide real-time timing information, enabling the elimination of timing margins preserved for PVT variations. However, the increased number of monitors and the short-path issue result in significant overhead. In this brief, a low-cost in-situ mechanism, intersection timing prediction and path activation detection (ITP-PAd), is proposed. It performs timing monitoring and path activation detection at the intersection of critical paths. Additionally, critical path replica (CPr) is introduced to support the ITP-PAd. A low-overhead 12-transistor (12-T) transition detector (Td) is designed to detect timing information and path activation, which operates stably at a sub-threshold voltage of 0.26 V. Furthermore, a method for selecting the minimum intersection points of critical paths has been proposed to reduce the number of insertion *** on an ArM Cortex-M0 microcontroller in 22nm technology, this approach reduces the insertion rate from 13.4% to 1.1%, with a total area overhead of only 1.3%. Measurements show that the chip's power consumption is reduced by 36.9% to 51.1% over a voltage range of 0.42 V to 0.8 V.

关键词： Monitoring Clocks delays Latches Power demand Logic Accuracy Voltage measurement Temperature sensors Temperature measurement Adaptive voltage scaling (AVS) process voltage and temperature (PVT) variations timing prediction timing monitoring activation detection transition detector

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Stacked gate-all-around nanosheet transistors with full-air-spacers for reducing parasitic capacitance to improve device and circuit performance

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MICrOELECTrONICS JOUrNAL 2025年 156卷

作者： Li, Lianlian Cao, Lei Zhang, Xuexiang Li, Qingkun Wu, Zhenhua Zhang, Meihe Bao, Yunjiao Wang, Peng Jiang, renjie du, Anyan Zhan, Qinzhu Yin, Huaxiang Chinese Acad Sci Integrated Circuit Adv Proc R&D Ctr Inst Microelect Beijing 100029 Peoples R China Chinese Acad Sci State Key Lab Fabricat Technol Integrated Circuits Inst Microelect Beijing 100029 Peoples R China Univ Chinese Acsdemy Sci Sch Integrated Circuits Beijing 100049 Peoples R China Zhejiang Univ Sch Phys Hangzhou 310000 Peoples R China

In this paper, we propose a full-air-spacers (FAS, air spacers and air inner spacers) technique and a feasible fabrication approach on gate all around (GAA) nanosheet field-effect-transistors (NSFETs) by a backside selective etching (BSE). Compared with NSFETs with SiNx spacers and low-kappa spacers, the FAS NSFETs exhibit no obvious degradation in dC characteristics, but show enormous improvements in AC characteristics and circuit benefits. The FAS technology provides 79.40 % reduction in effective capacitance and 75.71 % reduction in intrinsic delay. Moreover, the power consumption is reduced by 60.84 % at the same frequency, while the frequency gain is increased by 87.50 % at the same power consumption on the 17-stage ring oscillators (rOs). In addition, the FAS NSFETs-based 6T static random memories (SrAMs) cell has achieved 44.26 % and 82.46 % decrease in read time and write time, while 8.40 % and 4.54 % improvement in read noise tolerance and write noise tolerance, compared to the SiNx-NSFETs-based 6T-SrAM cell.

关键词： Full-air-spacer (FAS) Gate-all-around (GAA) Backside selective etching (BSE) effective capacitance ring oscillators (rOs) Static random memories (SrAMs)

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Enhanced Thermal Stability and reduced Specific Contact resistivity in Titanium-Based Ohmic Contact With an Ultra-Thin Molybdenum Interlayer

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTrON dEVICE LETTErS 2024年第7期45卷 1281-1284页

作者： Chen, Xu Xu, Jing Mao, Shujuan He, Yanping Gao, Jianfeng Liu, Weibing Sun, Xianglie Wang, Guilei Zhao, Chao Luo, Jun Chinese Acad Sci Integrated Circuit Adv Proc R&D Ctr Beijing 100029 Peoples R China Chinese Acad Sci Inst Microelect Key Lab Fabricat Technol Integrated Circuits Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuits Beijing 100049 Peoples R China Beijing Superstring Acad Memory Technol Beijing Peoples R China

This investigation reveals a practical method for improving thermal stability and reducing the specific contact resistivity (rho c) of titanium-based Ohmic contact. Inserting an ultrathin molybdenum (Mo) layer, with thicknesses ranging from 3 to 10 & Aring;, between titanium (Ti) and heavily doped silicon (Si) substrates effectively impedes the further diffusion of Si into the metal layer. Mo silicide contributes to lowering the temperature required for the formation of the C54-phase Ti silicide by 50 degrees C to 100 degrees C and facilitates the emergence of the low-resistance phase C54-TiSi2. Experimental evidence indicates that the insertion of thinner Mo layers significantly reduces rho c , which remains around the order of 10(-8) Omega & sdot;cm(2) after extensive annealing at 750 degrees C for 30 minutes.

关键词： Thermal stability Annealing Silicides Silicon Conductivity Thermal resistance random access memory Titanium silicide molybdenum interlayer thermal stability contact resistivity

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