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Ciphertext-Policy Attribute-Based Encryption with Short Keys

Chinese Journal of Electronics 2025年第4期23卷 655-660页

作者： Peng Xu Yong Tang Wenbin Jiang Hai Jin Deqing Zou Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

Ciphertext-policy attribute-based encryption (CP-ABE) allows a user with some attributes to decrypt the ciphertexts associated with these attributes. Though several CP-ABE schemes with the constant size ciphertext were proposed to reduce the communication cost, their master public and secret keys still have the size linear in the total number of attributes. These schemes are unpractical for the attribute-scalable and many-attributes scenario. A new CP-ABE scheme is proposed. Each attribute is mapped to a mathematical value by a combination method. The master public and secret keys of the proposed CP-ABE scheme have the size linear in the binary size of a hash function's range. It has the comparable performance with existing schemes in the aspects like the time costs of encryption and decryption, the expressiveness of access policy and the provable security.

关键词： Costs Encryption

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Anole: A Lightweight and Verifiable Learned-Based Index for Time Range Query on Blockchain systems 28th

Anole: A Lightweight and Verifiable Learned-Based Index for...

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28th International Conference on Database systems for Advanced Applications, DASFAA 2023

作者： Chang, Jian Li, Binhong Xiao, Jiang Lin, Licheng Jin, Hai National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

ISBN: (纸本)9783031306365

Time range query is essential to facilitate a wide range of blockchain applications such as data provenance in the supply chain. Existing blockchain systems adopt the storage-consuming tree-based index structure for better query performance, however, fail to efficiently work for most blockchain nodes with limited resources. In this paper, we propose Anole, a lightweight and verifiable time range query mechanism, to present the feasibility of building up a learned-based index to achieve high performance and low storage costs on blockchain systems. The key idea of Anole is to exploit the temporal characteristics of blockchain data distribution and design a tailored lightweight index to reduce storage costs. Moreover, it uses a digital signature to guarantee the correctness and completeness of query results by considering the learned index’s error bounds, and applies batch verification to further improve verification performance. Experimental results demonstrate that Anole improves the query performance by up to 10 × and reduces the storage overhead by 99.4 % compared with the state-of-the-art vChain+. © 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Blockchain

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Efficient Remote Memory Paging for Disaggregated Memory systems 1

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22nd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2022

作者： Wang, Tao Liu, Haikun Jin, Hai National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China

ISBN: (数字)9783031226779

ISBN: (纸本)9783031226762

Memory disaggregation has attracted increasing attention in recent years because it is a cost-efficient approach to scale memory capacity for applications in a data center. However, the latency of remote memory access is a major concern in disaggregated memory systems. This paper presents VANDI, a virtual memory paging mechanism that allows applications to use remote memory pools transparently. VANDI enables effective data caching and prefetching mechanisms to address the problem of high access latency in disaggregated memory systems. VANDI exploits a low-complexity cache replacement strategy to optimize the asynchronous staging queue so that the remote write latency can be significantly reduced. VANDI can also prefetch data in multi-granularity from a remote memory pool in an adaptive manner, and thus further improves the hit rate of the local cache to reduce the read latency of remote memory. Our extensive experiments using micro-benchmarks show that VANDI can improve the performance of typical remote paging system–Infiniswap by up to 15 × –102 ×. VANDI can also improve the performance of state-of-the-art disaggregated memory system–Valet by 1.2 × –2.7 ×. For typical machine learning workloads, VANDI can achieve 20% to 80% performance improvement compared with the state-of-the-art Valet. © 2023, Springer Nature Switzerland AG.

关键词： Paging systems

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Fast Parallel Recovery for Transactional Stream Processing on Multicores 40

Fast Parallel Recovery for Transactional Stream Processing o...

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40th IEEE International Conference on Data Engineering, ICDE 2024

作者： Zhao, Jianjun Liu, Haikun Zhang, Shuhao Duan, Zhuohui Liao, Xiaofei Jin, Hai Zhang, Yu School of Computer Science and Technology Huazhong University of Science and Technology National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab Wuhan China School of Computer Science and Engineering Nanyang Technological University Singapore

ISBN: (纸本)9798350317152

Transactional stream processing engines (TSPEs) have gained increasing attention due to their capability of processing real-time stream applications with transactional semantics. However, TSPEs remain susceptible to system failures and power outages. Existing TSPEs mainly focus on performance improvement, but still face a significant challenge to guarantee fault tolerance while offering high-performance services. We revisit commonly-used fault tolerance approaches in stream processing and database systems, and find that these approaches do not work well on TSPEs due to complex data dependencies. In this paper, we propose a novel TSPE called MorphStreamR to achieve fast failure recovery while guaranteeing low performance overhead at runtime. The key idea of MorphStreamR is to record intermediate results of resolved dependencies at runtime, and thus eliminate data dependencies to improve task parallelism during failure recovery. MorphStreamR further mitigates the runtime overhead by selectively tracking data dependencies and incorporating workload-aware log commitment. Experimental results show that MorphStreamR can significantly reduce the recovery time by up to 3.1 x while experiencing much less performance slowdown at runtime, compared with other applicable fault tolerance approaches. © 2024 IEEE.

关键词： Fault tolerance

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SharDAG: Scaling DAG-Based Blockchains Via Adaptive Sharding 40

SharDAG: Scaling DAG-Based Blockchains Via Adaptive Sharding

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40th IEEE International Conference on Data Engineering, ICDE 2024

作者： Cheng, Feng Xiao, Jiang Liu, Cunyang Zhang, Shijie Zhou, Yifan Li, Bo Li, Baochun Jin, Hai School of Computer Science and Technology Huazhong University of Science and Technology National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab China Hong Kong University of Science and Technology Hong Kong University of Toronto Canada

ISBN: (纸本)9798350317152

Directed Acyclic Graph (DAG)-based blockchain (a.k.a distributed ledger) has become prevalent for supporting highly concurrent applications. Its inherent parallel data structure accelerates block generation significantly, shifting the bottleneck from performance to storage scalability. An intuitive solution is to apply state sharding that divides the entire ledger (i.e., transactions and states) into multiple shards. While each node only stores proportional transactions, it suffers from the challenges of storing and ensuring the processing consistency of cross-shard transactions. In this paper, we propose SharDAG, a new mechanism that leverages adaptive sharding for DAG-based blockchains to achieve high performance and strong consistency. The key idea of SharDAG is to exploit unique characteristics -silent assets -and design a lightweight processing mechanism based on avatar account caching. Furthermore, we design a Byzantine resilient cross-shard verification mechanism with a theoretically optimal number of participating nodes, which guarantees the consistency and security of avatar account aggregation. Our comprehensive evaluations on real-world workloads demonstrate that SharDAG presents up to 3.8 x throughput improvement compared to the state-of-the-art and reduces the storage overhead of cross-shard transactions. © 2024 IEEE.

关键词： Blockchain

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Seer: Accelerating Block chain Transaction Execution by Fine-Grained Branch Prediction 51st

Seer: Accelerating Block chain Transaction Execution by Fine...

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51st International Conference on Very Large Data Bases, VLDB 2025

作者： Zhang, Shijie Cheng, Ru Liu, Xinpeng Xiao, Jiang Jin, Hai Li, Bo National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China Department of Computer Science and Engineering Hong Kong University of Science and Technology Hong Kong

Increasingly popular decentralized applications (dApps) with complex application logic incur significant overhead for executing smart contract transactions, which greatly limits public block chain performance. Pre-executing transactions off the critical path can mitigate substantial I/O and computation costs during execution. However, pre-execution does not yield any state transitions, rendering the system state inconsistent with actual execution. This inconsistency can lead to deviations in pre-execution paths when processing smart contracts with multiple state-related branches, thus diminishing pre-execution effectiveness. In this paper, we develop Seer, a novel public block chain execution engine that incorporates fine-grained branch prediction to fully exploit pre-execution effectiveness. Seerpredicts state-related branches using a two-level prediction approach, reducing inconsistent execution paths more efficiently than executing all possible branches. To enable effective reuse of pre execution results, Seer employs checkpoint-based fast-path execution, enhancing transaction execution for both successful and unsuccessful predictions. Evaluations with realistic block chain workloads demonstrate that Seer delivers an average of 27.7× transaction-level speedup and an overall 20.6× speedup in the execution phase over vanilla Ethereum, outperforming existing block chain execution acceleration solutions. © 2025, VLDB Endowment, All rights reserved.

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LibAMM: Empirical Insights into Approximate computing for Accelerating Matrix Multiplication 38

LibAMM: Empirical Insights into Approximate Computing for Ac...

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38th Conference on Neural Information Processing systems, NeurIPS 2024

作者： Zeng, Xianzhi Jiang, Wenchao Zhang, Shuhao National Engineering Research Center for Big DataTechnology and System Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China Nanyang Technological University Singapore Singapore University of Technology and Design Singapore

Matrix multiplication (MM) is pivotal in fields from deep learning to scientific computing, driving the quest for improved computational efficiency. Accelerating MM encompasses strategies like complexity reduction, parallel and distributed computing, hardware acceleration, and approximate computing techniques, namely AMM algorithms. Amidst growing concerns over the resource demands of large language models (LLMs), AMM has garnered renewed focus. However, understanding the nuances that govern AMM's effectiveness remains incomplete. This study delves into AMM by examining algorithmic strategies, operational specifics, dataset characteristics, and their application in real-world tasks. Through comprehensive testing across diverse datasets and scenarios, we analyze how these factors affect AMM's performance, uncovering that the selection of AMM approaches significantly influences the balance between efficiency and accuracy, with factors like memory access playing a pivotal role. Additionally, dataset attributes are shown to be vital for the success of AMM in applications. Our results advocate for tailored algorithmic approaches and careful strategy selection to enhance AMM's effectiveness. To aid in the practical application and ongoing research of AMM, we introduce LibAMM -a toolkit offering a wide range of AMM algorithms, benchmarks, and tools for experiment management. LibAMM aims to facilitate research and application in AMM, guiding future developments towards more adaptive and context-aware computational solutions. © 2024 Neural information processing systems foundation. All rights reserved.

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Towards High-throughput and Low-latency Billion-scale Vector Search via CPU/GPU Collaborative Filtering and Re-ranking 23

Towards High-throughput and Low-latency Billion-scale Vector...

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23rd USENIX Conference on File and Storage Technologies, FAST 2025

作者： Tian, Bing Liu, Haikun Tang, Yuhang Xiao, Shihai Duan, Zhuohui Liao, Xiaofei Jin, Hai Zhang, Xuecang Zhu, Junhua Zhang, Yu National Engineering Research Center for Big Data Technology and System Service Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology China Huawei Technologies Co. Ltd. China

ISBN: (纸本)9781939133458

Approximate nearest neighbor search (ANNS) has emerged as a crucial component of database and AI infrastructure. Ever-increasing vector datasets pose significant challenges in terms of performance, cost, and accuracy for ANNS services. None of modern ANNS systems can address these issues simultaneously. In this paper, we present FusionANNS, a high-throughput, low-latency, cost-efficient, and high-accuracy ANNS system for billion-scale datasets using SSDs and only one entry-level GPU. The key idea of FusionANNS lies in CPU/GPU collaborative filtering and re-ranking mechanisms, which significantly reduce I/O operations across CPUs, GPU, and SSDs to break through the I/O performance bottleneck. Specifically, we propose three novel designs: (1) multi-tiered indexing to avoid data swapping between CPUs and GPU, (2) heuristic re-ranking to eliminate unnecessary I/Os and computations while guaranteeing high accuracy, and (3) redundant-aware I/O deduplication to further improve I/O efficiency. We implement FusionANNS and compare it with the state-of-the-art SSD-based ANNS system-SPANN and GPU-accelerated in-memory ANNS system-RUMMY. Experimental results show that FusionANNS achieves 1) 9.4-13.1× higher query per second (QPS) and 5.7-8.8× higher cost efficiency compared with SPANN;2) and 2-4.9× higher QPS and 2.3-6.8× higher cost efficiency compared with RUMMY, while guaranteeing low latency and high accuracy. © 2025 FAST. All Rights Reserved.

关键词： Collaborative filtering

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An Efficient Graph Accelerator with Distributed On-Chip Memory Hierarchy 22nd

An Efficient Graph Accelerator with Distributed On-Chip Mem...

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22nd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2022

作者： Zheng, Ran Jiang, Yingxin Wang, Yibo Su, Yongbo Zheng, Long Yao, Pengcheng Liao, Xiaofei Jin, Hai National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China Zhejiang Lab Hangzhou311121 China

ISBN: (纸本)9783031226762

Graph processing has evolved and expanded swiftly with artificial intelligence and big data technology. High-Bandwidth Memory (HBM), which delivers terabyte-level memory bandwidth, has opened up new development possibilities for FPGA-based graph accelerators. However, despite the tremendous expansion of underlying hardware capabilities, existing graph accelerators have not benefited too much. In this paper, we observe that the uniformed on-chip memory hierarchy is the key to the low scalability of existing graph accelerators. We present a novel graph accelerator with a distributed on-chip memory hierarchy called GraphS. The on-chip memory of GraphS is divided into numerous tiny blocks, each of which is assigned to only one Processing Element (PE). Different PEs are connected through a scalable network-on-chip (NoC). For realistic graphs with power-law properties, a degree-aware preprocessing method is designed to balance the workload among different PEs. Our results with various graph algorithms demonstrate that GraphS can outperform state-of-the-art ForeGraph by up to 21.84 ×. © 2023, Springer Nature Switzerland AG.

关键词： Network-on-chip

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P3DC:Reducing DRAM Cache Hit Latency by Hybrid Mappings

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Journal of Computer Science & technology 2024年第6期39卷 1341-1360页

作者： Ye Chi Ren-Tong Guo Xiao-Fei Liao Hai-Kun Liu Jianhui Yue National Engineering Research Center for Big Data Technology and System Wuhan 430074China Services Computing Technology and System Laboratory Wuhan 430074China Cluster and Grid Computing Laboratory Wuhan 430074China School of Computer Science and Technology Huazhong University of Science and TechnologyWuhan 430074China School of Big Data and Internet Shenzhen Technology UniversityShenzhen 518118China Department of Computer Science Michigan Technological UniversityHoughton 49931-1295U.S.A.

Die-stacked dynamic random access memory(DRAM)caches are increasingly advocated to bridge the performance gap between the on-chip cache and the main *** fully realize their potential,it is essential to improve DRAM cache hit rate and lower its cache hit *** order to take advantage of the high hit-rate of set-association and the low hit latency of direct-mapping at the same time,we propose a partial direct-mapped die-stacked DRAM cache called *** design is motivated by a key observation,i.e.,applying a unified mapping policy to different types of blocks cannot achieve a high cache hit rate and low hit latency *** address this problem,P3DC classifies data blocks into leading blocks and following blocks,and places them at static positions and dynamic positions,respectively,in a unified set-associative *** also propose a replacement policy to balance the miss penalty and the temporal locality of different *** addition,P3DC provides a policy to mitigate cache thrashing due to block type *** results demonstrate that P3DC can reduce the cache hit latency by 20.5%while achieving a similar cache hit rate compared with typical set-associative caches.P3DC improves the instructions per cycle(IPC)by up to 66%(12%on average)compared with the state-of-the-art direct-mapped cache—BEAR,and by up to 19%(6%on average)compared with the tag-data decoupled set-associative cache—DEC-A8.

关键词： die-stacked dynamic random access memory(DRAM) cache set-associative direct-mapped hit latency

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