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Nano-optical imaging of WSe2 waveguide modes revealing light-exciton interactions

Physical Review B 2016年第8期94卷 081402(R)-081402(R)页

作者： Z. Fei M. E. Scott D. J. Gosztola J. J. Foley, IV J. Yan D. G. Mandrus H. Wen P. Zhou D. W. Zhang Y. Sun J. R. Guest S. K. Gray W. Bao G. P. Wiederrecht X. Xu Center for Nanoscale Materials Argonne National Laboratory Lemont Illinois 60439 USA Department of Physics and Astronomy Iowa State University Ames Iowa 50011 USA Department of Physics University of Washington Seattle Washington 98195 USA Department of Chemistry William Paterson University Wayne New Jersey 07470 USA Materials Science and Technology Division Oak Ridge National Laboratory Oak Ridge Tennessee 37831 USA Department of Materials Science and Engineering University of Tennessee Knoxville Tennessee 37996 USA Advanced Photon Source Argonne National Laboratory Lemont Illinois 60439 USA State Key Laboratory of ASIC and System Department of Microelectronics Fudan University Shanghai 200433 China Department of Materials Science and Engineering University of Washington Seattle Washington 98195 USA

We report on a nano-optical imaging study of WSe2 thin flakes with scanning near-field optical microscopy (NSOM). The NSOM technique allows us to visualize in real space various waveguide photon modes inside WSe2. By tuning the excitation laser energy, we are able to map the entire dispersion of these waveguide modes both above and below the A exciton energy of WSe2. We found that all the modes interact strongly with WSe2 excitons. The outcome of the interaction is that the observed waveguide modes shift to higher momenta right below the A exciton energy. At higher energies, on the other hand, these modes are strongly damped due to adjacent B excitons or band-edge absorptions. The mode-shifting phenomena are consistent with polariton formation in WSe2.

关键词： Excitons Photonics Polaritons

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An 11-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation

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Journal of Semiconductors 2014年第8期35卷 151-157页

作者：顾蔚如叶凡任俊彦 State Key Laboratory of ASIC & System Microelectronics Science and Technology Innovation Platform Fudan University

： This paper presents an l 1-bit 22-MS/s 0.6-mW successive approximation register （SAR） analog-to- digital converter （ADC） using SMIC 65-nm low leakage （LL） CMOS technology with a 1.2 V supply voltage. To reduce the total capacitance and core area the split capacitor architecture is adopted. But in high resolution ADCs the parasitic capacitance in the LSB-side would decrease the linearity of the ADC and it is hard to calibrate. This paper proposes a parasitic capacitance compensation technique to cancel the effect with no calibration circuits. Moreover, dynamic circuits are used to minimize the switching power of the digital logic and also can reduce the latency time. The prototype chip realized an 11-bit SAR ADC fabricated in SMIC 65-nm CMOS technology with a core area of 300 × 200 μm2. It shows a sampling rate of 22 MS/s and low power dissipation of 0.6 mW at a 1.2 V supply voltage. At low input frequency the signal-to-noise-and-distortion ratio （SNDR） is 59.3 dB and the spurious-free dynamic range is 72.2 dB. The peak figure-of-merit is 36.4 fJ/conversion-step.

关键词： analog-to-digital converter dynamic circuits parasitic capacitor compensation successive approxi-mation register

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A 30-GHz to 39-GHz mm-Wave low-power injection-locked frequency divider in 65nm CMOS

A 30-GHz to 39-GHz mm-Wave low-power injection-locked freque...

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International Conference on asic

作者： Guangyao Zhou Shunli Ma Fazhi An Ning Li Fan Ye Junyan Ren State Key Laboratory of ASIC and Systems Fudan University Shanghai China Department of Microelectronics Fudan University Shanghai China

In this paper, a wide locking range and low power Injection-Locked Frequency Divider (ILFD) is presented. Compared to conventional structure, 2-b digital controlled capacitor array is introduced to extend its locking range. Meanwhile, the tail current source is eliminated to reduce the supply voltage and enlarge the output voltage swing. The post-simulations show that the total locking-range is from 29.7GHz to 39.2GHz when input power is 0dBm. While operating at highest frequency band, the output power is 1.3dBm, and phase noise at 1-MHz offset are -156.9dBc/Hz. The divider core draws a RMS current of 8.5mA under a supply voltage of 0.65V. The total divider with 50Ω output buffer takes up 540μm×205μm without probe pad in TSMC 65-nm CMOS process.

关键词： Frequency conversion Phase noise Layout Capacitors Q-factor Capacitance

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A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network

A 1.5-GS/s 5-bit interpolating ADC with offset averaging and...

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International Conference on asic

作者： Rongjin Xu Yongzhen Chen Mingshuo Wang Ning Li Fan Ye Junyan Ren State Key Laboratory of ASIC and Systems Fudan University Shanghai China Department of Microelectronics Fudan University Shanghai China

In this paper, a 1.5-GS/s 5-bit interpolating analog-to-digital converter (ADC) with offset averaging and interpolating sharing resistors network (OAISRN) is presented. The proposed OAISRN is based on conventional flash ADC and the concept of zero crossing points in folding and interpolating architecture. In order to reduce power dissipation yet to make a high performance, it removes half of preamplifiers and ensures matching by using offset averaging and 2x-interpolation sharing resistors network behind the initial zero crossing points generators array. Implementation of the OAISRN is explained in detail and its impact on signal bandwidth is discussed. The interpolating ADC in TSMC 65 nm process achieves SNDR of 27.8 dB and SFDR of 37.7 dB for 745 MHz input frequency located at 1.5 GS/s in postsimulation. The power consumption is 9.6 mW under a supply voltage of 1.2 V.

关键词： Interpolation Resistors Preamplifiers Power demand Bandwidth Logic arrays Clocks

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Investigation of in situ boron-doping in sige source/drain layer growth for PMOS devices

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Journal of Nanomaterials 2015年第1期2015卷

作者： Zhong, Min Chen, Shou Mian Zhang, David Wei State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai200433 China Shanghai IC RandD Center Co. Ltd. Shanghai201210 China

Embedded SiGe (eSiGe) source/drain (S/D) was studied to enhance PMOS performance. Detailed investigations concerning the effect of GeHand Bgas flow rate on the resultant Boron-doping of the SiGe layer (on a 40 nm patterned wafer) were carried out. Various SiGeB epitaxial growth experiments were realized under systematically varying experimental conditions. key structural and chemical characteristics of the SiGeB layers were investigated using Secondary Ion Mass Spectroscopy (SIMS), nanobeam diffraction mode (NBD), and Transmission Electron Microscopy (TEM) itself. Furthermore, I on / I off performances of 40 nm PMOS transistors are also measured by the Parametric Test systems for the semiconductor industry. The results indicate that the ratio between GeHand Bgas flow rates influences not only the Ge and Boron content of the SiGeB layer, but also the PMOS channel strain and the morphology of the eSiGe S/D regions which directly affect PMOS performance. In addition, the mechanism of Boron-doping during SiGe layer growth on the pattern wafer is briefly discussed. The results and discussion presented within this paper are expected to contribute to the optimization of eSiGe stressor, aimed for advanced CMOS devices. © 2015 Min Zhong et al.

关键词： Si-Ge alloys

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Feature-scale Simulations of Particulate Slurry Flows in Chemical Mechanical Polishing by Smoothed Particle Hydrodynamics

Feature-scale Simulations of Particulate Slurry Flows in Che...

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第十七届全国流体力学数值方法研讨会

作者： DongWang Sihong Shao ChanghaoYan Wei Cai Xuan Zeng State Key Laboratory of ASIC and System School ofMicroelectronics Fudan University Shanghai 201203 China State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai 201203 China LMAM and School of Mathematical Sciences Peking University Beijing 100871China Department of Mathematics and Statistics University of North Carolina at CharlotteCharlotte NC 28223 USA

Chemical mechanical polishing (CMP) is a key process widely used in semiconductor manufacturing industry to provide local and global planarity of silicon *** this talk, the mechanisms of material removal in CMP process are investigated in detail by the smoothed particle hydrodynamics (SPH) method where an new, efficient and parallel neighbour search method based on plane sweep algorithm is proposed at the same *** feature-scale behaviours of slurry flow,rough pad, wafer defects, moving solid boundaries, slurry-abrasive interactions and abrasive collisions are modeled and simulated.

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Efficient modeling and implementation of cryptographic processor using UML and systemC

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Journal of Computational Information systems 2015年第10期11卷 3809-3820页

作者： Ma, De Chu, Chaoqiang Li, Chunshu Meng, Jianyi Yan, Xiaolang Institute of Microelectronics CAD Hangzhou Dianzi University Hangzhou China Institute of VLSI Design Zhejiang University Hangzhou China Belgium State Key Laboratory of ASIC and System Fudan University Shanghai China

To mitigate the increasing design complexity of very large scale integrated circuits (VLSI), the abstraction level design engineers work on has to be raised. In this paper, we propose an efficient UML-and systemC-based design flow with performance, area and power coestimation at early stages and apply it to RSA and ECC crypto-Processor implementation. It is divided into several sections. Firstly, the UML class diagram is used to describe the target architecture and the UML sequence and state diagrams are used to describe the dynamic behavior of the design. Secondly, systemC behavior models are translated from the UML models semi-automatically and TLM models are refined from systemC behavior models. During systemC behavior and TLM modeling process, the estimation methodology of performance, power and area is combined to facilitate architecture exploration. This can avoid extensive redesign, reduce cost/time and achieve good trade-off in power, area and performance. Thirdly, a hybrid simulation of TLM and RTL models is proposed to validate the refinement from TLM to RTL. The experimental results with performance, power, and area estimation at different abstraction levels are adopted to demonstrate the efficiency of the proposed design flow for RSA and ECC crypto-processor design. ©, 2015, Binary Information Press. All right reserved.

关键词： Integrated circuit design

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Latency-Optimized Stochastic LDPC Decoder for High-Throughput Applications

Latency-Optimized Stochastic LDPC Decoder for High-Throughpu...

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IEEE International Symposium on Circuits and systems

作者： Di Wu Yun Chen Qichen Zhang Lirong Zheng Xiaoyang Zeng Yeong-luh Ueng State Key Laboratory of ASIC & system Fudan University Shanghai China Department of Electrical Engineering National Tsing Hua University Taiwan

ISBN: (纸本)9781479983926

Stochastic decoding can be applied to Low-Density Parity-Check codes in order to achieve high throughput with less area. However, most architectures suffer from large decoding latencies, due to the mechanism of stochastic computation. In this paper, three novel strategies, including the LUT-based initialization, the posterior-information-based hard decision and the Bit-Flipping-based post processing, are proposed in order to reduce decoding latency and hence improve throughput. For the standard IEEE 802.3an (2048, 1723) code, simulation indicates 75.7% reduction in average decoding cycles at 4.5 dB with satisfied bit error rate. Moreover, hardware implementation shows that the area of variable node units is reduced significantly in SMIC 65 nm technology.

关键词： Bit-Flipping Algorithm Low-Density Parity-Check Codes High-throughput Decoder Stochastic decoding

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Differential Power Analysis on Dynamic Password Token Based on SM3 Algorithm, and Countermeasures

Differential Power Analysis on Dynamic Password Token Based ...

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International Conference on Computational Intelligence and Security

作者： Limin Guo Lihui Wang Qing Li Jun Yu Peng Luo Shanghai Fudan Microelectronics Group Co. Ltd State Key Laboratory of ASIC and System Shanghai China Fudan University Shanghai China Commercial Cryptography Testing Center Beijing China

Dynamic password technology is widely utilized for identity authentication, which depends on using hash functions, such as SM3. And SM3 hash algorithm is based on the mixing of different group operations, such as XOR and addition modulo 232. In this paper, we present two original first-order differential power analysis attacks on dynamic password token based on SM3 algorithm. The two proposed DPA attacks are against XOR and addition modulo 232 operation respectively. Experimental results show that dynamic password token based on SM3 algorithm is vulnerable to side channel attacks, no matter implemented in software or hardware. We also provide a masked implementation of the algorithm, which is designed to avoid those proposed attacks.

关键词： Heuristic algorithms Algorithm design and analysis Software algorithms Software Mathematical model Power demand Hardware

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Polarization fatigue in antiferroelectric (Pb,La)(Zr,Ti)O3 thin films: The role of the effective strength of driving waveform

Polarization fatigue in antiferroelectric (Pb,La)(Zr,Ti)O3 t...

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作者： Geng, Wenping Liu, Yang Lou, Xiaojie Zhang, Fuping Liu, Qida Dkhil, Brahim Zhang, Ming Ren, Xiaobing He, Hongliang Jiang, Anquan State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai200433 China Multi-disciplinary Materials Research Center Frontier Institute of Science and Technology State Key Laboratory for Mechanical Behavior of Materials Xi'An Jiaotong University Xi'an710049 China Laboratoire Structures Propriétés et Modélisation des Solides UMR 8580 CNRS-Ecole Centrale Paris Grande Voie des Vignes Châtenay-Malabry-Cedex92295 France National Key Laboratory of Shock Wave and Detonation Physics Institute of Fluid Physics CAEP Mianyang621900 China State Key Laboratory for Strength and Vibration of Mechanical Structures Xi'An Jiaotong University 710049 China

In this study, a critical parameter termed as "effective electric strength" is developed to depict polarization fatigue in antiferroelectric thin films. Specifically, the effect of pulse width, frequency, and magnitude of driving voltage (or field) on polarization fatigue of antiferroelectric (Pb,La)(Zr,Ti)O3 (PLZT) thin films was investigated in detail. By transforming all the waveforms with different pulse-widths/voltages/frequencies into their effective electric strength, a strong correlation between the effective strength and the degree of polarization fatigue in the PLZT films is revealed. For instance, it was found that appreciable fatigue usually occurs when the effective strength is larger than or equal to the voltage of phase transition from antiferroelectric phase to ferroelectric phase. In addition, it is shown that the films are more prone to fatigue for a lower frequency of the same effective strength. Our findings could be well explained in the framework of the local phase decomposition arising from switching induced charge injection. © 2015 Elsevier Ltd and Techna Group S.r.l. All rights reserved.

关键词： Electronic properties

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