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Design, Automation and Test in Europe Conference and Exhibition

作者： Xuanzeng Lihong Feng Yangfeng Su Wei Cai D. Zhou C. Chiang ASIC & System State-key Laboratory Microelectronics Department Fudan University Shanghai China Mathemaitics Department Fudan University Shanghai China Department of Mathematics University of North Carolina Charlotte Charlotte NC USA Departemnt of Electrical Engineering University of Texas Dallas Richardson TX USA Mountain View Synopsys Inc. CA USA

ISBN: (纸本)9783981080100

In this paper, a wavelet based approach is proposed for the model order reduction of linear circuits in time domain. Compared with Chebyshev reduction method, the wavelet reduction approach can achieve smaller reduced order circuits with very high accuracy, especially for those circuits with strong singularities. Furthermore, to compute the basis function coefficient vectors, a fast Sylvester equation solver is proposed, which works more than one or two orders faster than the vector equation solver employed by Chebyshev reduction method. The proposed wavelet method is also compared with the frequency domain model reduction method, which may loose accuracy in time domain. Both theoretical analysis and experiment results have demonstrated the high speed and high accuracy of the proposed method

关键词： Wavelet domain Chebyshev approximation Frequency domain analysis Integrated circuit interconnections Equations Transfer functions Mathematical model Application specific integrated circuits Laboratories microelectronics

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Some Solutions for Writing Current Reduction and High Density Application of Phase Change Memory

Some Solutions for Writing Current Reduction and High Densit...

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2006 8th International Conference on Solid-state and Integrated Circuit Technology

作者： Yinyin Lin Jie Feng Yaifei Cai Hangbing Lv Feifei Liao Xin Liu Tingao Tang Baowei Qiao Yunfeng Lai Yi Zhang Bingchu Cai Bomy Chen Department of Microelectronics ASIC and System State Key Lab.Fudan University Research Institute of Micro/Nanometer Technology Shanghai Jiao Tong University Silicon Storage Technology Inc.1171 Sonora CourtSunnyvaleCA94086USA

＜正＞High writing current is the bottle-neck of PCM application and efforts focus on merely materials doping to improve crystal resistivity,novel structure to decrease active area *** some solutions of our group are ...

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Effect of Trimethyl Aluminium Surface Pretreatment on Atomic Layer Deposition Al2O3 Ultra-Thin Film on Si Substrate

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Chinese Physics Letters 2005年第9期22卷 2418-2421页

作者：徐敏卢红亮丁士进孙亮张卫汪礼康 State Key Laboratory of ASIC and System Department of Microelectronics Fudan University Shanghai 200433

Ultra-thin Al2O3 dielectric films have been deposited on Si substrates by using trimethyl aluminium （TMA） and water as precursors in an atomic layer deposition （ALD） system. Growth of the interracial layer between ultra-thin Al2O3 and the Si substrate is effectively suppressed by a long-time TMA surface pretreatment of the Si substrate prior to A1203 atomic layer deposition. High resolution transmission electron microscopy （TEM） images show that the thickness of the interracial layer is reduced to be 0.5nm for the sample with TMA pretreatment lasting 3600s. The x-ray photoelectron spectroscopy results indicate that the A1203 film deposited on the TMApretreated Si surface exhibits very good thermal stability. However, a hysteresis of about 50mV is observed in the C- V curve of the samples with the TMA pretreatment.

关键词： NUCLEATION SILICON GROWTH OXIDES

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Non-holonomy in im torque control

Non-holonomy in im torque control

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International Workshop on Advanced Motion Control (AMC)

作者： B. Crcar P. Cafuta G. Stumberger H.R. Cortes A.M. Stankovic Electrical Engineering Department Al-Azhar University Cairo Egypt School of Engineering Science and Design Glasgow Caledonian University Glasgow Scotland UK Valley Higher Institute for Engineering and Technology Science Valley Academy Cairo Egypt Tech. University of Delft THE NETHERLANDS State Key Laboratory of ASIC & System Fudan University Shanghai CHN

In the paper IM torque control is studied as an example of non-holonomic system with drift terms. Following the famous Brockett integrator problem several control propositions are introduced. The paper extends the control scheme from the state to the output control in several steps. By introducing adjusted amplitude, frequency and phase modulation of the IM stator current vector, the rotor flux linkage vector is implicitly forced to generate required periodic orbits that satisfy nonholonomic constraint. Improvements in the transient feedback performance, maximal steady-state efficiency, avoidance of singularities and sufficient robustness are actually achieved by making the current modulation dependent from the torque error signal. In the contrast with the original work instead of global only local stability could be assured. Simulation and experimental results illustrate main characteristics of the proposed control

关键词： Torque control Frequency Phase modulation Stators Rotors Couplings Orbits Feedback Steady-state Robustness

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New model of ferroelectric capacitor based on C-V, I-V, Q-V Characteristics

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors

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Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors 2005年第5期26卷 984-989页

作者： Chen, Xiaoming Tang, Ting'ao State Key Laboratory of ASIC and System Department of Microelectronics Fudan University Shanghai 200433 China

A new model is developed for describing the electrical behavior of ferroelectric capacitors. By modeling the ferroelectric capacitor as a switching capacitor (dipole capacitor) in series with a non-switching capacitor (linear capacitor) and this dipole capacitor as a collection of dipoles with a top electrode and a bottom electrode, and by assuming the probability density functions of dipoles' coercive voltages (positive and negative) as t-distribution according to experiment results of ferroelectric capacitors' C-V characteristic, the C-V, I-V, and Q-V expressions of ferroelectric capacitors are derived, 'and these expressions are described with only six parameters. The simulated results from these expressions are quite fitted with experiment results.

关键词： Capacitors

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An Universal Hierarchical FPGA Partitioning Algorithm

An Universal Hierarchical FPGA Partitioning Algorithm

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2005 6th International Conference on asic

作者： Yuanfeng Chen Pushan Tang Jinmei Lai Jiarong Tong ASIC & System State Key Laboratory Microelectronic DepartmentFudan University

HFPGA(Hierarchical FPGA) is a common FPGA architecture in *** paper presents an improved partition algorithm based on previous hierarchical FPGA partitioning *** algorithm combines the simulated annealing algorithm with ratio-cut method to decide the level of the multi-level multi-way *** consider the number of cut lines while partitioning CLBs into cluster,so as to achieve a better partitioning result and improve the usage rate in HFPGA,then optimize the FPGA performance.

关键词： HFPGA Hierarchical FPGA partition

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FPGA Placement Using Genetic Algorithm with Simulated Annealing

FPGA Placement Using Genetic Algorithm with Simulated Anneal...

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2005 6th International Conference on asic

作者： M.Yang A.E.A.Almaini L.Wang Pengjun Wang State Key Laboratory of ASIC & System School of MicroelectronicsFudan University Institute of Circuits and Systems Ningbo University

A mixed Genetic Algorithm and Simulated Annealing (GASA) algorithm is used for the placement of symmetrical *** proposed algorithm includes 2 stage *** the first stage process it optimizes placement solutions globally using *** the second stage process it locally improves *** overcomes the slow convergence of genetic algorithm in the late phase of the process of genetic *** results show that GASA consumes less CPU time than GA and could achieve performance as good as versatile placement and routing tool in terms of placement cost.

关键词： FPGA Placement Using Genetic Algorithm with Simulated Annealing

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A universal hierarchical FPGA partitioning algorithm

A universal hierarchical FPGA partitioning algorithm

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International Conference on asic

作者： Yuanfeng Chen Pushan Tang Jinmei Lai Jiarong Tong ASIC & System State Key Laboratory Microelectronic Department Fudan University Shanghai China

HFPGA (hierarchical FPGA) is a common FPGA architecture in industry. The paper presents an improved partition algorithm based on previous hierarchical FPGA partitioning works. The algorithm combines the simulated annealing algorithm with ratio-cut method to decide the level of the multi-level multi-way partitioning. We consider the number of cut lines while partitioning CLBs into cluster, so as to achieve a better partitioning result and improve the usage rate in HFPGA, then optimize the FPGA performance

关键词： Field programmable gate arrays Partitioning algorithms Clustering algorithms Simulated annealing Routing Circuit simulation Data structures Application specific integrated circuits Laboratories microelectronics

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High-performance systolic arrays for band matrix multiplication

High-performance systolic arrays for band matrix multiplicat...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Yun Yang Wenqing Zhao Y. Inoue Graduate School of Information Production and Systems Waseda University Kitakyushu Japan ASIC & System State-Key-Laboratory Microelectronics Department Fudan University Shanghai China

Band matrix multiplication is widely used in DSP systems. However, for band matrix multiplication, the traditional Kung-Leiserson systolic array cannot be realized with high cell-efficiency. Three high-performance band matrix multiplication systolic arrays (BMMSA) are presented, based on the ideas of "matrix compression" and "super pipelining". These new systolic arrays are realized by compressing the data matrix skillfully and adjusting the operating sequence carefully. The results show that the best systolic array for band matrix multiplication uses almost 100% of the processing elements (PE) in each step. Also, these modifications increase the operation speed, and, at best spend, only 1/3 of the processing time is required to complete the multiplication operation.

关键词： Systolic arrays Digital signal processing Computer architecture Concurrent computing Throughput Delay Yarn Application specific integrated circuits Production systems microelectronics

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Preserving the film coefficient as a parameter in the compact thermal model for fast electrothermal simulation

Preserving the film coefficient as a parameter in the compac...

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作者： Feng, Lihong H. Rudnyi, Evgenii B. Korvink, Jan G. IEEE ASIC and System State-key Laboratory Microelectronics Department Fudan University Shanghai 200433 China University of Freiburg D-79085 Freiburg Germany University of Freiburg Freiburg Germany Department of Examination Board Faculty of Applied Sciences IMTEK ETH Zurich Ritsumeikan University of Kusatsu Japan Kyoto University Kyoto Japan Technical Program Committees

Compact thermal models are often used during joint electrothermal simulation of microelectromechanical systems (MEMS) and circuits. Formal model reduction allows generation of compact thermal models automatically from high-dimensional finite-element models. Unfortunately, it requires fixing a film coefficient employed to describe the convection boundary conditions. As a result, compact models produced by model reduction do not comply with the requirements of being boundary condition independent. In the present paper, the authors suggest an approach of successive series expansion with respect to the film coefficient as well as to the frequency during model reduction that allows to overcome the problem and keep the film coefficient as a symbolic parameter in the reduced model. The approach is justified with a numerical example of electrothermal simulation of a microthruster unit. © 2005 IEEE.

关键词： Thermoanalysis

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