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Microwave, MTT-S International Symposium

作者： Yatao Peng Youpeng Zhong Zechen Guo Song Liu Dapeng Yu State Key Lab. of Analog and Mixed-Signal VLSI IME/ECE of FST University of Macau China Shenzhen International Quantum Academy China Shenzhen Institute for Quantum Science and Engineering SUSTech China

The measurement of the fast-increasing number of qubits necessitates the use of a large number of specialized cryogenic low-noise amplifiers (LNAs).). This work presents a broadband LNA designed with discrete GaAs HEMT components which operate well at ~3.6 K temperature. The dual-frequency optimum noise matching network and output matching elements of the first stage were employed to optimize the equivalent noise temperature (NT) and the input return loss in a wideband. Measurement results at 3.6 K ambient temperature show that the LNA achieved an equivalent NT of <12 K, and a gain of >30 dB in the 3.5 GHz to 7.5 GHz band with a minimum of 5 Kelvin at ~6.5 GHz. The best visibility of ~0.891 is achieved when using the LNA to observe a superconducting transmon qubit without using a JPA.

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A-40°C-125 °C 0.4-μA Low-Noise Bandgap Voltage Reference With 0.8-mA Load Driving Capability Using Shared Feedback Resistors

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2022年第10期69卷 4033-4037页

作者： Zhang, Zhaobo Zhan, Chenchang Wang, Lidan Law, Man-Kay Univ Macau State Key Lab Analog & Mixed Signal VLSI IME Macau Peoples R China Univ Macau FST ECE Macau Peoples R China Southern Univ Sci & Technol Sch Microelect Shenzhen 518055 Peoples R China Southern Univ Sci & Technol Minist Educ Engn Res Ctr Integrated Circuits Next Generat Com Shenzhen 518055 Peoples R China

This brief presents a fully integrated low-power, low noise bandgap reference (BGR) with load driving capability. With the BGR core resistors functioning as the feedback network of the current sourcing power transistor, the proposed BGR saves chip area, reduces noise while supporting current load driving. The circuit is implemented in two different processes for performance comparison, namely the 0.18 mu m RF CMOS and the BCD mixed-signal CMOS processes. Measurement results from chip samples of the two processes show similar performances, with an average temperature coefficient (TC) of 27.1ppm/degrees C over -40 similar to 125 degrees C at a 1.8-V supply. The corresponding measured coefficient of variation (sigma/mu) is around 0.3%, and the load driving capability can be up to 800 mu A. By reusing the feedback resistors, the chip prototype achieved a low noise density of 1.92 mu V/v root Hz, 285nV/v root Hz and 4nV/v root Hz at 10 Hz, 10 kHz and 100 kHz, respectively, while consuming a quiescent current of 396nA. The measured power supply rejection (PSR) is -39dB at 5Hz and -45dB at 1MHz. The influence of load current on PSR has also been analyzed and verified.

关键词： Bandgap reference (BGR) low dropout regulator (LDO) low power low noise two wafers low-cost Internet of Things (IoT)

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A Multimode CMOS Vision Sensor With On-Chip Motion Direction Detection and Simultaneous Energy Harvesting Capabilities (vol 22, pg 12808, 2022)

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IEEE SENSORS JOURNAL 2022年第17期22卷 17318-17318页

作者： Wu, Jiangchao Lu, Xin Law, Man-Kay Jiang, Yang Liu, Liyuan Mak, Pui-In Martins, Rui P. Univ Macau State Key Lab Analog & Mixed Signal VLSI Inst Microelect Macau Peoples R China Univ Macau FST ECE Macau Peoples R China Chinese Acad Sci State Key Lab Superlattices & Microstruct Inst Semicond Beijing 100083 Peoples R China Univ Chinese Acad Sci Ctr Mat Sci & Optoelect Engn Beijing 100049 Peoples R China

In the above article [1], unfortunately, there was a printing error in Fig. 11(b). This error affects the correct frame difference (FD) operation with Fig. 11(a) for generating the motion vector image in Fig. 11(c), b... 详细信息

关键词： Printing Vision sensors System-on-chip Energy harvesting

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A 12.87-dB Gain 10.5-dBm OPldB60-to-66-GHz LNA in 0.15-μm GaAs pHEMT Technology

A 12.87-dB Gain 10.5-dBm OPldB60-to-66-GHz LNA in 0.15-μm G...

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2022 IEEE the Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2022

作者： Li, Xuefeng Wang, Yuting Wu, Tianxiang Chen, Yong Ren, Junyan Ma, Shunli School of Microelectronics Fudan University State Key Laboratory of ASIC and System Shanghai China State Key Laboratory of ASIC and System School of Information Science and Technology Fudan University Shanghai China University of Macau State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST Macao China

ISBN: (纸本)9781665450690

This paper presents a V-band low noise amplifier (LNA) implemented in a 0.15-μm Gallium Arsenide (GaAs) pseudomorphic high electron-mobility transistor (pHEMT) technology. The LNA adopts a three-stage common-source (CS) topology. Each transistor has a bias circuit, and the microstrip-line inductor is used to realize the input noise matching network, the interstage, and the output matching network. Circuit simulations show that our LNA scores a 12.87-dB small-signal gain, the 3-dB bandwidth ranges from 60 GHz to 66 GHz, and the current consumption is 30 mA under a 5-V supply voltage. Its noise figure is 5.9 dB, and the output 1-dB compression point is 10.5 dBm. The chip area is 1.32× 1.5mm2. © 2022 IEEE.

关键词： Low noise amplifiers

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A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC

A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shapin...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Li, Ke Sin, Sai-Weng Qi, Liang Zhao, Weibing Wang, Guoxing Martins, R. P. Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau IME ECE FST Macau Peoples R China Shanghai Jiao Tong Univ Dept Micronano Elect Shanghai Peoples R China Amicro Semicond Co Ltd Zhuhai Peoples R China

ISBN: (纸本)9781665484855

This paper presents a hybrid CT/DT 0-2 multi-stage noise-shaping (MASH) delta-sigma modulator (DSM) with a passive noise-shaping successive approximation register (NS-SAR) ADC as the 2(nd) stage. The overall architecture is simple and robust. The front-end stage employs the continuous-time (CT) operation to perform coarse quantization and provide inherent anti-aliasing and easy driving. The back-end stage uses a second-order NS-SAR architecture, which excels at PVT robustness, power efficiency, and scaling friendliness. It also results in large relaxation of matching issues between the analog and the digital domains compared with conventional CT-MASH. Behavioral simulation results demonstrate the effectiveness and robustness of the proposed hybrid MASH architecture.

关键词： Hybrid ADC delta-sigma modulator (DSM) multi-stage noise-shaping (MASH) noise-shaping successive approximation register (NS-SAR)

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A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted analog Pre-Distorter (DAAPD) Reconfigurable Linearization Technique

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2021年第11期68卷 3381-3385页

作者： Mariappan, Selvakumar Rajendran, Jagadheswaran Chen, Yong Mak, Pui-In Martins, Rui P. Univ Sains Malaysia Collaborat Microelect Design Excellence Ctr Engn Campus George Town 11800 Malaysia Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau IME ECE FST Macau Peoples R China

This brief presents a CMOS power amplifier (PA) employing a digitally-assisted analog pre-distorter (DAAPD) reconfigurable linearization technique to reduce the back-off output power (PBO) for multiband operation. The proposed DAAPD optimizes the interstage load impedance between the driver and the main stage by changing the transconductance of the driver amplifier and its active load. We also utilize the DAAPD to optimize the PA when subjected to process-voltage-temperature (PVT) variations. Fabricated in 130-nm CMOS, the DAAPD-PA operates from 1.7 to 2.7 GHz with a 3 dB back-off output power efficiency of 35% to 38% while fulfilling the stringent adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) requirements of a 20-MHz 16-QAM LTE signal. With a continuous wave (CW) signal, the DAAPD-PA achieves a maximum output power of 27 to 28 dBm across frequencies of interest with supply headroom of 3.3 V. Finally, the DAAPD-PA covers 20 LTE bands with reduced back-off output power.

关键词： Power amplifiers Power generation Transconductance Voltage control Tuning Long Term Evolution Transistors Power amplifier (PA) CMOS digitally-assisted analog predistorter (DAAPD) back-off output power (PBO) adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) power-added efficiency (PAE) long-term evolution (LTE)

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A 4-bit mixed-signal MAC Array with Swing Enhancement and Local Kernel Memory

A 4-bit Mixed-Signal MAC Array with Swing Enhancement and Lo...

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IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Yu, Wei-Han Giordano, Massimo Doshi, Rohan Zhang, Minglei Mak, Pui-In Martins, Rui P. Murmann, Boris Univ Macau State Key Lab Analog & Mixed Signal VLSI IME Macau Peoples R China Univ Macau FST ECE Macau Peoples R China Stanford Univ Stanford CA 94305 USA

ISBN: (纸本)9781665424615

Modern deep neural networks require energy- and area-efficient multi-bit multiply-accumulate (MAC) functions. In-memory computing (IMC) with analog accumulation has shown the potential to outperform purely digital solutions but lacks efficient multi-bit computation. In this work, we explore the design of a mixed-signal, charge-sharing compute array that performs 4-bit MAC operations within one clock cycle. Its key features include 7x4 bit kernel memory in each MAC cell, as well as a per-kernel binary combiner that simplifies the unit cell design and enables efficient in-column ADC integration. In addition, it leverages a differential switching scheme that improves the signal swing by 4x relative to single-ended schemes, thereby reducing ADC energy. Post-layout simulations in 28 nm CMOS indicate an energy efficiency of 6.4 fJ/MAC and a compute density of 3.17 TOPS/mm(2) for an input activation vector size of 160.

关键词： Deep neural networks hardware accelerators in-memory computing mixed-signal integrated circuits switched capacitor circuits

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A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common-Mode Resonator and Intrinsic Differential 2nd-Harmonic Output

A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Yunbo Huang Yong Chen Chaowei Yang Pui-In Mak Rui P. Martins State Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST University of Macau Macao China On leave from Instituto Superior Técnico Universidade de Lisboa Portugal

This paper presents an 8-to-10GHz CMOS voltage-controlled oscillator (VCO) with common-mode (CM) resonance. It features a nested 8-shape inductor-based CM resonator with intrinsic differential $2^{\text{nd}}$ harmonic extraction. The mutual coupling of the main tank and CM resonator is negligible due to the reversal magnetic field, which avoids the additional chip area occupation of the explicit CM inductor. The VCO prototyped in 65-nm CMOS scores a −136.7-dBc/Hz PN with 10-MHz offset at 9.97 GHz, consuming 4 mW of power with a standard supply voltage of 1-V. The achieved peak Figure-of-Merit (FOM) is 190.6 dBc/Hz at 10-MHz offsets. Over a 22.9% tuning range, the VCO upholds a consistent FOM of >188.5 dBc at a 10-MHz offset. The core area is 0.116 mm 2 ,

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A 0.11-pJ/Bit True Random Number Generator Based on a Clocked Current-Starved Inverter

A 0.11-pJ/Bit True Random Number Generator Based on a Clocke...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Kai Cheng Chaowei Yang Rui P. Martins Pui-In Mak Yong Chen State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST University of Macau Macao China Instituto Superior Técnico Universidade de Lisboa Lisboa Portugal (Now) Department of Electronic Engineering Tsinghua University Beijing China

ISBN: (数字)9798350361834

ISBN: (纸本)9798350361841

This paper presents a clocked current-starved inverter-based true random number generator (TRNG) in 65-nm CMOS. The design of the TRNG uses inverter noise amplification and quantification through a sense latch. We add two extra transistors to a regular inverter to construct a current-starved inverter, used to remove the bias of the raw TRNG sequence generated by charge injection and SL offset. An adaptive calibration algorithm in conjunction with successive approximation register logic provides the biasing to the clocked current-starved inverter. Our TRNG occupies an area of only 0.0026 mm 2 and scores an energy efficiency of 0.11 pJ/bit for a 10 Mb/s random sequence with a 0.5 V supply. It can operate efficiently across a 0.5-1.4 V. Our TRNG is able to pass all the National Institute of Standards and Technology tests without requiring post-processing.

关键词： Voltage NIST Throughput Inverters Generators Energy efficiency Robustness Calibration Transistors Random sequences

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A Capacitorless Flipped-Voltage-Follower-Based Low-Dropout Regulator Incorporating Adaptive-Compensation Buffer

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (vlsi) SYSTEMS 2025年第5期33卷 1422-1426页

作者： Tan, Yee-Chyan Ramiah, Harikrishnan Hatta, S. F. Wan Muhamad Lim, Chee-Cheow Martins, Rui P. Mak, Pui-In Chen, Yong Univ Tunku Abdul Rahman Fac Engn & Green Technol Dept Elect Engn Kampar 31900 Perak Malaysia Univ Malaya Fac Engn Ctr Res Ind 4 0 CRI4 0 Dept Elect Engn Kuala Lumpur 50603 Malaysia Asia Pacific Univ Technol & Innovat Sch Engn Kuala Lumpur 57000 Malaysia Univ Macau State Key Lab Analog & Mixed Signal VLSI IME ECE FST Macau Peoples R China Univ Lisbon Inst Super Tecn P-1649004 Lisbon Portugal Tsinghua Univ Dept Elect Engn Beijing 100190 Peoples R China

This brief presents an output-capacitorless low-dropout (OCL-LDO) regulator based on flipped-voltage-follower (FVF) and dual pMOS pass transistors. An adaptive-compensation buffer (ACB) dynamically regulates the operation of the pass transistors. Specifically, when the load current falls below 5 mA, only the smaller pass transistor is activated;otherwise, both pass transistors are engaged, thereby simultaneously mitigating the minimum load current requirement for FVF architecture and extending the load current ranging from 0 to 30 mA while maintaining stability without an external load capacitor. At 1.15-V supply voltage and 0-mA load current, the quiescent current is 6 mu A. The output voltage is 1.0 V with a dropout voltage of 0.15 V. Measurements show that with a load current stepping from 0 to 30 mA at an edge time of 100 ns, the output voltage undershoot is 0.2 V with a recovery time of 200 ns while achieving a load regulation of 0.23 mV/V. Our OCL-LDO is fabricated in a 180-nm CMOS with an active area of 0.031 mm(2).

关键词： Transistors Logic gates Circuit stability Stability criteria Transient analysis Voltage measurement Voltage control Very large scale integration Regulation Poles and zeros CMOS flipped voltage follower (FVF) output-capacitorless low-dropout (OCL-LDO)

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