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IEEE Asian Conference on Solid-state Circuits (ASSCC)

作者： Kai Xing Yan Zhu Rui Paulo Martins Chi-Hang Chan State-Key Laboratory of Analog and Mixed Signal VLSI DECE/FST University of Macau Macau China On leave from Instituto Superior Técnico Universidade de Lisboa Portugal

ISBN: (数字)9798350376326

ISBN: (纸本)9798350376333

With the advent of WLAN technologies, over 320 MHz BW and $\gt 65 \mathrm{~dB}$ DR ADCs become indispensable to support newly developed WiFi standards. Three classic solutions can reach the said targets but involve various compromises (Fig. 1 top). CT MASH ADCs [1] rely on a relatively high OSR $(\geqslant 7)$ as well as NS order to accommodate the adequate noise spectral density (NSD), limiting the energy efficiency. The CT pipeline (PIPE) ADC [2–3] obviates the feedback loop and its 1st stage energy effectively provides preliminary quantization, residue generation, amplification, and filtering. However, the backend CT quantization can be power-hungry [2] [4]. The DT NS pipeline ADC offers a low-power alternative [5] but loses the intrinsic anti-aliasing (AA) ability from its CT counterparts. This work hybridizes CT and DT NS PIPE, gaining the pros from the CT PIPE front-end and DT PIPE backend. Together with the Single amplifier biquad (SAB) - Residue Amplifying Filter (RAF) and NS TD-QTZ, the C/DT PIPE ADC demonstrates superior energy efficiency over CT MASH ADCs with 320MHz BW.

关键词： Multi-stage noise shaping Quantization (signal) Limiting Filtering Pipelines Noise Energy efficiency Solid state circuits Wireless fidelity Standards

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A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and analog Non-Uniform Quantization

A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial ...

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Guoqiang Xin Fei Tan Junde Li Junren Chen Wei-Han Yu Ka-Fai Un Rui P. Martins Pui-In Mak The State-Key Laboratory of Analog and Mixed-Signal VLSI/IME and FST-ECE University of Macau Macao China on-leave from the Instituto Superior Técnico UL Portugal

ISBN: (数字)9798350387179

ISBN: (纸本)9798350387186

analog computing-in-memory (CIM) macro has been widely used in various machine learning (ML) applications, which parallelly perform energy- and area-efficient matrix-vector multiplication (MVM) operations. Compared with digital CIM, analog CIM has shown great efficiency on multi-bit MVM computations. However, the analog approaches accumulate the MVM results on the voltage domain, different accumulation lengths and data sparsity cause distinct signal swing degradation and variation. Hence, the analog-to-digital converter (ADC) readout circuit requires more power and area to trade off with the noise and comparator offset. In this paper, we proposed a partial sum boosting (PSB) method to give $4.6\times$ to $22.8\times$ signal swing enhancement for multi-bit MVM, which mitigates severe ADC overhead for analog CIM. Furthermore, multi-bit 5T-SRAMs with diverse voltage supplies realize multi-bit uniform/non-uniform sign-and-magnitude (SNM) weight representation and save up to $38.8\times$ SRAMs static power dissipation. The chip was fabricated in 28nm CMOS technology and measured a throughput density of 89.04 TOPS $/\text{mm}^analog$ and energy efficiency of 219.5 TOPSIW under 3-bit activation, 4-bit SNM weight with no truncation 5-bit partial sum readout condition.

关键词： Weight measurement Semiconductor device measurement Quantization (signal) Density measurement Energy measurement In-memory computing Boosting

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A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration 35

A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Inde...

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35th Symposium on vlsi Circuits, vlsi Circuits 2021

作者： Zhang, Minglei Zhu, Yan Chan, Chi-Hang Martins, Rui P. University of Macau State-Key Laboratory of Analog and Mixed-Signal Vlsi Ime China

ISBN: (纸本)9784863487796

This paper demonstrates a background timing skew calibration for the time-interleaved (TI) ADCs using a direct time-based estimation to facilitate the input-independent and fast convergence features. It suppresses the timing spurs of a 20GS/s 8× TI-ADC below 50dB at a Nyquist input regardless of the calibrating input condition with 24 calibration cycles. The 8b time-domain TI-ADC achieves a 91.3fJ/conv.-step FoMWalden and >16GHz bandwidth. © 2021 JSAP.

关键词： Calibration

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A Single-Channel 14b 500 MS/s Pipelined-SAR ADC with Reference Ripple Mitigation Techniques and Adaptive-Biased Floating Inverter Amplifier

A Single-Channel 14b 500 MS/s Pipelined-SAR ADC with Referen...

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2022 IEEE Asian Solid-state Circuits Conference, A-SSCC 2022

作者： Jiang, Wenning Zhu, Yan Chan, Chi-Hang Martins, Rui State-Key Laboratory of Analog and Mixed-Signal VLSI/IME-DECE/FST University of Macau China Frontier Institute of Chip and System/Zhangjiang Fudan International Innovation Center Fudan University Shanghai China On Leave Instituto Superior Técnico Universidade de Lisboa Portugal

ISBN: (数字)9781665471435

ISBN: (纸本)9781665471435

The accuracy and speed of the residue handover process are crucial in two-step architectures. Advanced residue amplifiers (RAs) [1]-[5] enable a fast residue handover operation in Pipelined ADCs but often necessitate calibrations. Furthermore, with a short acquisition time and a large capacitive DAC in high-resolution designs, it is challenging to ensure the reference voltage of the DAC is sufficiently settled before the amplification. Eventually, the reference buffer (RBUF) calls for a considerable power and/or area overhead. This work introduces an adaptive-biased floating inverter amplifier (ABFIA) as the RA in a single-channel 14b 500MS/s Pipelined-SAR (Pipe-SAR) ADC, reaching a 16x calibration-free gain in a short time. Further, by leveraging a Reference Ripple Cancellation (RRC)coarse SAR ADC and Reference Ripple Neutralization (RRN)assisted RBUF, it avoids large sizing multi-input-pair in the comparator and the stringent timing requirement in conventional RRN [6] and RRC [7] technique, respectively. © 2022 IEEE.

关键词： Pipelines

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A 1224 V-Input HV-LV-Separated Hybrid SC PoL Converter With 355 mWmm³ Power Density at 3 A Load Current and 15.2 mm³ Power Passives

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IEEE TRANSACTIONS ON POWER ELECTRONICS 2023年第12期38卷 15109-15114页

作者： Zhang, Xiongjie Ma, Qiaobo Zhao, Anyang Jiang, Yang Law, Man-Kay Jiang, Junmin Takamiya, Makoto Martins, Rui P. Mak, Pui-In Univ Macau State Key Lab Analog & Mixed Signal VLSI IME Macau 999078 Peoples R China Univ Macau Dept ECE FST Macau 999078 Peoples R China Southern Univ Sci & Technol Dept Elect & Elect Engn Shenzhen 518055 Peoples R China Univ Tokyo Inst Ind Sci Tokyo 1538505 Japan Univ Lisbon P-1649004 Lisbon Portugal

This letter presents a high-power-density point-of-load dc-dc converter for 12/24 V input applications, using the proposed high voltage-low voltage separated hybrid switched-capacitor (SC) topology. By incorporating inductors between the SCnetworks in HV/LVdomains, the design achieves reduced inductor dc current (I-L,I- DC) at small voltage conversion ratios (VCRs), optimized switching and conduction losses, and extended duty ratio range, enabling the use of small-sized inductors with higher dc resistance and resulting in a compact system volume. LV switches handle most of the current conduction, reducing switching losses and silicon area for higher on-chip power density. The fabricated converter, using a 180-nm BCD process, generates 0.8-1.8 V output from 12/24 V inputs with a 3-A maximum load. Measured results show total I-L,I- DC of 1.2 A at VCR 0.075 and 2 A load. The converter achieves a peak power density of 355mW/mm(3) with a power passive volume of 15.2 mm(3). Peak efficiencies are 85% at 12 V input and 84.2% at 24 V input.

关键词： DC-DC high step-down hybrid inductor current reduction power density switched-capacitor (SC)

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A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS

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IEEE JOURNAL OF SOLID-state CIRCUITS 2022年第5期57卷 1358-1371页

作者： Zhao, Xiaoteng Chen, Yong Wang, Lin Mak, Pui-In Maloberti, Franco Martins, Rui P. Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau 999078 Peoples R China Univ Macau IME ECE FST Macau 999078 Peoples R China Univ Pavia Dept Elect I-27100 Pavia Italy Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This article reports a half-rate single-loop bang-bang clock and data recovery (BBCDR) circuit without the need of reference and frequency detector (FD). Specifically, we propose a deliberate-current-mismatch charge-pump pair to enable fast and robust frequency acquisition without identifying the frequency error polarity. This technique eliminates the need for a complex high-speed data or clock path during the frequency acquisition, resulting in significant power savings. Prototyped in 28-nm CMOS, the BBCDR circuit automatically tracks a four-level pulse-amplitude modulation (PAM-4) input between 47.6 and 58.8 Gb/s. The core area is 0.056 mm(2). Both the achieved energy efficiency (0.22-0.25 pJ/bit) and the acquisition speed [9.8 (Gb/s)/mu s] compare favorably with the state of the art.

关键词： Clocks Artificial neural networks Voltage-controlled oscillators Detectors Very large scale integration Time-frequency analysis Hardware Bang-bang clock and data recovery (BBCDR) charge pump (CP) CMOS four-level pulse-amplitude modulation (PAM) frequency detector (FD) half-rate negative net current (NNC) positive net current (PNC) reference-less and zero net current (ZNC)

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Piezoelectric Energy Harvesting Interface Using Self-Bias-Flip Rectifier and Switched-PEH DC-DC for MPPT

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IEEE JOURNAL OF SOLID-state CIRCUITS 2024年第7期59卷 2248-2259页

作者： Li, Zhen Wang, Jing Law, Man-Kay Du, Sijun Liang, Junrui Cheng, Xu Han, Jun Zeng, Xiaoyang Chen, Zhiyuan Fudan Univ State Key Lab Integrated Chips & Syst Shanghai Peoples R China Fudan Univ Sch Microelect Shanghai Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI IME & FST Macau Peoples R China Delft Univ Technol Dept Microelect NL-2628 CD Delft Netherlands ShanghaiTech Univ Sch Informat Sci & Technol Shanghai 201210 Peoples R China ShanghaiTech Univ Shanghai Engn Res Ctr Energy Efficient & Custom AI Shanghai 201210 Peoples R China

This article proposes a novel eight-phase self bias-flip piezoelectric energy harvesting interface with charge recycling and reusing (SBFRR) and a switched-piezoelectric energy harvester (PEH) dc-dc (SPDC) converter. The proposed scheme innovatively utilizes the inherent capacitors (C-P) of four PEHs as energy sources, flying capacitors, and flipping capacitors for time-sharing reuse to achieve both a high-voltage flipping and dc-dc conversion efficiency, while avoiding the use of extra energy reservoirs. The design is fully integrated and fabricated in standard 0.18-mu m CMOS. Measurement result demonstrates that the voltage flipping efficiency of up to 80% is achieved. Compared with the ideal full-bridge rectifier (FBR), the measured maximum output power improving rate (MOPIR) can be increased to 4.88x. In addition, with the four C-P serving as flying capacitors to achieve SPDC conversion for maximum power point track (MPPT), an MOPIR of >3.5x can be maintained with a PEH input voltage from 0.78 to 4.9 V.

关键词： Energy harvesting flipping efficiency fully integrated maximum output power improving rate (MOPIR) maximum power point track (MPPT) multi-input piezoelectric self-bias-flip switched-piezoelectric energy harvester (PEH) dc-dc (SPDC)

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A 3-Phase Resonant Switched-Capacitor Converter for Data Center 48-V Rack Power Distribution

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2021年第6期68卷 2714-2724页

作者： Wang, Chuang Lu, Yan Sun, Nan Martins, Rui P. Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau 999078 Peoples R China Univ Macau FST DECE Macau 999078 Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI & FST DE Macau 999078 Peoples R China Univ Lisbon Inst Super Tecn Lisbon Portugal

Since the power consumption of data centers keeps increasing, a 48-V rack power distribution system replaces the conventional 12-V power bus to reduce the power delivery IR losses. Meanwhile, the 48 V needs conversion into 1 V or lower at the point-of-load for microprocessors. A 48V-to-12V DC-DC converter can serve as a first stage between the huge gap of 48V-to-1V, in a two-stage voltage regulator module (VRM). Thus, this paper presents a 3-phase resonant switched-capacitor (3 Phi-ReSC) converter as the first stage of the VRM. Different from the reported solutions, 3-phase resonant operation reduces the current stress across each small-size GaN switch, and thus improves the power conversion efficiency. In addition, we also present the theoretical analysis and design procedures for the 3 Phi-ReSC converter. We demonstrated the proposed 3 Phi-ReSC converter with a 98% peak power efficiency at an output current of about 1 A, with a maximum output current of 10 A.

关键词： Data center rack power distribution resonant converter switched-capacitor dc-dc converter 3-phase operation 48V

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Fully Integrated Frequency-Tuning Switched-Capacitor Rectifier for Piezoelectric Energy Harvesting

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IEEE JOURNAL OF SOLID-state CIRCUITS 2023年第8期58卷 2337-2348页

作者： Xie, Chao Zhao, Guangshu Ma, Yuan Law, Man-Kay Zhang, Milin Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Univ Macau Inst Microelect IME Fac Sci & Technol Elect & Comp Engn FST ECE State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Tsinghua Univ Beijing Natl Res Ctr Informat Sci & Technol Inst Precis Med Dept Elect Engn Beijing 100084 Peoples R China

This article proposed the first fully integrated synchronous electric-charge extraction (SECE) interface, featuring: 1) no external passive components and the smallest normalized on-chip capacitance;2) an increased energy-extraction efficiency;and 3) a maximized extracted power regardless of the input and output conditions. With the multi-step soft-charging (MSC) technique relaxing energy-extraction conduction loss, we can effectively minimize the on-chip capacitance while improving the energy-extraction efficiency. To further depress the control loss, the positive current selector (PCS) is proposed to realize digital rectification during charge extraction. With the SECE strategy facilitating output independence, we further investigate an automatic phase and amplitude tuning method to enable maximumpower-point tracking (MPPT) over an extended input excitation bandwidth. Fabricated in 0.18-mu m CMOS, the proposed rectifier achieves a maximum output power improving rate (MOPIR) of 8.14x with V-D = 0.12 V and a 405% bandwidth improvement over the piezoelectric energy harvester (PEH) natural bandwidth.

关键词： Bandwidth extension efficiency energy harvesting (EH) integrated maximum-power-point tracking (MPPT) piezoelectric soft-charging switched-capacitor (SC) synchronous electric-charge extraction (SECE)

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A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector 8

A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recover...

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8th IEEE Nordic Circuits and Systems Conference (NorCAS)

作者： Ge, Xinyi Chen, Yong Wang, Lin Qi, Nan Mak, Pui-In Martins, Rui P. Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau IME FST ECE Macau Peoples R China Chinese Acad Sci Inst Semicond Beijing Peoples R China

ISBN: (数字)9798350345506

ISBN: (纸本)9798350345506

This paper reports a 28-Gb/s bang-bang clock and data recovery (CDR) circuit based on the proposed phase detector (BBPD) including four sample flip-flops, two combined XORs, and a voltage-to-current converter. We employ a charge-steering technique to minimize power consumption, inserting one additional branch with a combined XOR into the proposed BBPD, to detect all code types. The CDR prototype pulls-off a 523.7-fs jitter performance with 13.8-mW power consumption.

关键词： Charge steering clock and data recovery (CDR) bang-bang phase detector (BBPD) return-to-zero (RZ) non-return-to-zero (NRZ) quadrature voltage-controlled oscillator (QVCO) RZ-to-NRZ converter half rate CMOS

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