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SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

引用

作者： ZHOU Fei

标准号: US2019067447(A1)

Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing at least one fin on a semiconductor substrate;forming a stacked channel layer having at least one sacrificial layer on the fin and a channel layer on the sacrificial layer;forming a dummy gate structure on the stacked channel layer;forming openings in the stacked channel layer at both sides of the dummy gate structure;removing portions of the sacrificial layer under the dummy gate structure to form grooves on sidewall surfaces of the openings;and forming a protective layer in the grooves.

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SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF

SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF

引用

作者： ZHOU Fei

标准号: US2019067467(A1)

A method for fabricating a semiconductor structure includes providing a base substrate, including a substrate, a plurality of gate structures formed on the substrate, and a cap layer formed on the plurality of gate structures;removing the cap layer to form a trench on each gate structure;and forming a substitution layer in the trench. The dielectric constant of the substitution layer is smaller than the dielectric constant of the cap layer.

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SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

引用

作者： ZHOU Fei

标准号: US2019097020(A1)

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a substrate including a functional region and a blank region;and forming one or more active fins on the functional region of the substrate, and one or more sacrificial fins on the blank region of the substrate. The method also includes forming a dummy gate structure, across length portions of each active fin and each sacrificial fin;and forming an interlayer dielectric layer to fill a gap between adjacent dummy gate structures. In addition, the method includes forming a gate opening in the interlayer dielectric layer by removing the dummy gate structure. Further, the method includes removing at least a portion of the sacrificial fin in the gate opening;and forming a gate structure in the gate opening after removing the portion of the sacrificial fin in the gate opening.

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SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

引用

作者： ZHOU Fei

标准号: US2019067434(A1)

Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a fin material layer on the semiconductor substrate;forming an isolation material layer having a bandgap greater than a bandgap of the fin material layer on the fin material layer;and forming a stacked channel material layer on the isolation material layer. The stacked channel material layer includes a sacrificial material layer and a channel material layer on the sacrificial material layer. The method also includes etching the stacked channel material layer, the isolation material layer and the fin material layer to form fins protruding from the semiconductor substrate, an isolation layer on the fins and a stacked channel layer on the isolation layer. The stacked channel layer includes a sacrificial layer and a channel layer on the sacrificial material layer.

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SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF

SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF

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作者： ZHOU Fei

标准号: US2019067155(A1)

A semiconductor structure includes a substrate. The substrate includes a plurality of function regions and a plurality of heat-dissipation regions. Each heat-dissipation region is adjacent to at least one function region. The semiconductor structure also includes a plurality of active fin structures, protruding from the substrate of the plurality of function regions;a plurality of channel layers, each formed on an active fin structure;and a plurality of heat-dissipation fin structures, protruding from the substrate of the plurality of heat-dissipation regions.

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Analysis and modeling of self-heating effect in bulk FinFET

Analysis and modeling of self-heating effect in bulk FinFET

引用

2017 China Semiconductor technology International Conference, CSTIC 2017

作者： Lin, Shawn Li, Sensheng Shen, Li Ju, Jianhua Yu, Shaofeng Technology Research and Development Center SMIC Shanghai China

ISBN: (纸本)9781509066940

Self-heating effect in bulk FinFET is briefly studied in this paper. The layout dependence of thermal resistance and thermal capacitance are assumed and the correction method is proposed to improve the accuracy of thermal parameter. Measuring methods and their corresponding test structures are also summarized. Besides, two realization methods of self-heating effect for circuit simulation are also discussed. © 2017 IEEE.

关键词： SPICE

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Analysis and modeling of self-heating effect in bulk FinFET

Analysis and modeling of self-heating effect in bulk FinFET

引用

China Semiconductor technology International Conference (CSTIC)

作者： Shawn Lin SenSheng Li Li Shen Jianhua Ju Shaofeng Yu SMIC Technology Research and Development Center Shanghai China

ISBN: (纸本)9781509066957

关键词： Temperature measurement FinFETs Analytical models Logic gates Heating Reliability Temperature

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Fin bending mechanism investigation for 14nm FinFET technology

Fin bending mechanism investigation for 14nm FinFET technolo...

引用

China Semiconductor technology International Conference (CSTIC)

作者： Cheng Li Hai Zhao Gang Mao Advanced Technology Research and Development SMIC ATD Shanghai China

ISBN: (纸本)9781509066957

Beyond 14nm logical technologies, Fin structure becomes one of the common features and the most balance solution to improve MOSFET performance. Fin structure benefits electrical characteristics due to its narrow and tall properties, but it also easily suffers unwanted mechanical failure due to high aspect ratio. One of these typical mechanical failures, named fin bending, usually occurs during STI formation because of stress problem. This paper will discuss the possible factors and demonstrate the mechanism.

关键词： Annealing Mechanical factors Silicon

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Analysis of short channel effects for 14nm and beyond Si-bulk FinFET

Analysis of short channel effects for 14nm and beyond Si-bul...

引用

China Semiconductor technology International Conference (CSTIC)

作者： Xiaolei Yang Yong Li Xinyun Xie Shuai Zhang Zhaoxu Shen Fei Zhou Xin He Jie Zhao Gang Mao Anni Wang Jianhua Ju Advanced Technology Research and Development Center SMIC Shanghai China

As Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuit (IC) technology scales down to 14nm and sub-14nm node according to Moore's Law, Si-bulk FinFET has been demonstrated as one of the most promising device architectures due to higher transistor performance, larger density and lower leakage. However, as the gate length scales down continuously, short channel effect, mainly Vth roll-up/off, becomes a serious problem that needs to be solved urgently. In this paper, two mechanis ms, mainly work function modulation induced by Fluorine diffusion from tungsten to metal gate layer and high phosphorus in-situ doped source/drain epitaxy, are studied for N-type FinFET Vth roll up/off in detail, which is significant and meaningful in the development on 14nm and beyond FinFETs.

关键词： Logic gates Metals Fluorine FinFETs Epitaxial growth Phosphorus Threshold voltage

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Study of fin CD controllability for FinFET manufacturing

Study of fin CD controllability for FinFET manufacturing

引用

China Semiconductor technology International Conference (CSTIC)

作者： Hai Zhao Gang Mao Rex Yang Technology Research and Development SMIC Logic Technology and Development Center SMIC Shanghai China

In this paper, several steps which would affect CD variation or Fin CD loss were analyzed during FinFET manufacturing, and then we figured out the dominant ones causing CD loss. Finally, an optimization guideline for Fin CD control in process integration was suggested for better Fin CD controllability. It's not only good for Fin CD control, but also good for wide process margin to integrate smaller Fin CD beyond 20nm technology node.

关键词： Logic gates Performance evaluation FinFETs Industries Mass production Surface treatment Annealing

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