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37th IEEE VLSI Test Symposium (VTS)

作者： Zhang, Jianwei Gupta, Sandeep K. Halfond, William G. J. Univ Southern Calif Los Angeles CA 90007 USA

ISBN: (纸本)9781728111704

Test generation for digital hardware is highly automated, scalable (in practice), and provides high test quality. In contrast, current software automatic test data generation approaches suffer from low test quality or high complexity. While mutation-oriented constraint-based test data generation for software was proposed to generate high quality test data for real program bugs, all existing approaches require symbolic analysis for the whole program, and hence are not scalable even for unit testing, i.e., testing the lowest-level software modules. We propose a new method inspired by hardware d-algorithm and divide and conquer for software test data generation. To reduce runtime complexity and improve scalability, we combine global structural analysis and a sequence of small reusable symbolic analyses of parts of the program, instead of symbolically executing each mutated version of the entire program. We also propose a multi-pass test generation system to further reduce runtime complexity and compact test data. We compare our tools with one of the best software test generation tools (EvoSuite[20], which won the SBST 2017 tool competition) and demonstrate that our approach generates higher quality unit tests in a scalable manner and provides a compact set of tests.

关键词： test data generation for software d-algorithm ATPG mutation testing software testing

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A Comprehensive Test Pattern Generation Approach Exploiting the SAT Attack for Logic Locking

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IEEE TRANSACTIONS ON COMPUTERS 2023年第8期72卷 2293-2305页

作者： Zhong, Yadi Guin, Ujjwal Auburn Univ Dept Elect & Comp Engn Auburn AL 36849 USA

The need for reducing manufacturing defect escape in today's safety-critical applications requires increased fault coverage. However, generating a test set using commercial automatic test pattern generation (ATPG) tools that lead to zero-defect escape is still an open problem. It is challenging to detect all stuck-at faults to reach 100% fault coverage. In parallel, the hardware security community has been actively involved in developing solutions for logic locking to prevent IP piracy. In logic locking, locks are inserted in different locations of the netlist to modify the original functionality. Unless the correct key is programmed into the IC, the circuit functions incorrectly. Unfortunately, the Boolean satisfiability (SAT) based attack, introduced in (Subramanyan et al. 2015), can determine the secret key efficiently, and break different logic locking schemes. In this article, we propose a novel test pattern generation approach using the powerful SAT attack on logic locking. A stuck-at fault is modeled as a locked gate with a secret key, where it can effectively deduce the satisfiable assignment with reduced backtracks under key initialization of the SAT attack. The input pattern that determines the key is a test for the stuck-at fault. We propose two different approaches for test pattern generation. First, a single stuck-at fault is targeted, and a corresponding locked circuit with one key bit is created. This approach generates one test pattern per fault. Second, we consider a group of faults and convert the circuit to its locked version with multiple key bits. The inputs obtained from the SAT attack tool are the test set for detecting this group of faults. Our approach can find test patterns for all hard-to-detect faults that were previously undetected in commercial ATPG tools. The proposed test pattern generation approach can efficiently detect redundant faults as well. We demonstrate the effectiveness of the approach on ITC'99 benchmarks. The results show

关键词： ATPG d-algorithm Boolean satisfiability logic locking fault coverage

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Performance analysis of a 2-d EEG compression algorithm using an automatic seizure detection system

Performance analysis of a 2-D EEG compression algorithm usin...

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Asilomar Conference on Signals, Systems & Computers

作者： Hoda daou Fabrice Labeau Department of Electrical and Computer Engineering McGill University Montreal QUE Canada

ISBN: (纸本)9781467350501

A recently developed compression algorithm that uses dWT, SPIHT and smoothness transforms to compress EEG channels in 2-d proved to give very low distortion values for high compression ratios. Although Rd performance is a commonly used metric in signal compression, in medical signals, it is important to preserve important diagnostic information. In order to move towards such a diagnostics-oriented performance assessment, we propose in this paper a framework to evaluate the performance of EEG compression mechanisms in terms of post-compression seizure detection capability. In particular, we show that the above-mentioned 2-d algorithm can maintain diagnostic features down to bitrates of 2 bits per sample.

关键词： EEG dWT SPIHT Electroencephalography Compression algorithms compression ratio d-algorithm signal compression diagnostic message Seizures detection systems Bit rate

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Extended selection of switching target faults in CONT algorithm for test generation

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Journal of Electronic Testing: Theory and Applications (JETTA) 1990年第3期1卷 183-183页

作者： Takamatsu, Y. Kinoshita, K. Department of Computer Science Faculty of Engineering Ehime University Matsuyama Japan Department of Applied Physics Faculty of Engineering Osaka University Suita Japan

We describe an extended selection of switching target faults in the CONT algorithm. The main difficulty in test generation is the conflict that arises in the process of determining the signal values due to reconvergent fanouts. Conventional approaches for test generation change a signal value, which causes conflicts to another possible choice for backtracking. In the CONT algorithm, a strategy of switching target fault was proposed as a new backtracking mechanism. In this method, the target fault is switched to a new target fault instead of making an alternative assignment on the primary input value when a conflict occurs. A disadvantage of the CONT algorithm is that unjustified lines exist in the process of test generation. These unjustified lines make the procedure of switching targets complicated and restrict the possible choice in selecting the new target fault. In the new version of CONT, called CONT-2, we have removed the unjustified lines in the process of test generation and have extended to two target-fault types for switching targets. Implementing CONT-2 by a Fortran program, ISCAS85 benchmark circuits are examined. Experiments on a combined system with fault simulation followed by CONT-2 are also presented.

关键词： d-algorithm fault simulation fault target switching

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HEURISTIC CIRCUIT SIMULATION USING PROLOG

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INTEGRATION-THE VLSI JOURNAL 1985年第4期3卷 283-318页

作者： GULLICHSEN, E UNIV VICTORIA DEPT COMP SCIVICTORIA V8W 2Y2BCCANADA

Through the use of the logic programming language PROLOG, digital logic circuitry can be conveniently represented in predicate calculus in a manner amenable to various forms of computation. Axioms define the behavior of primitive gates in a given technology, and implications hierarchically characterize the behavior of non-primitive modules. Simulation of circuitry proceeds by theorem proving, viewed as constraint satisfaction. A PROLOG-based simulator is presented for the investigation of heuristics to efficiently solve problems of ‘backward’ simulation which arise in a number of areas, such as reasoning about fault isolation. The heuristic simulator can also serve as the basis for an elegant implementation of Roth's d-algorithm.

关键词： digital logic logic programming heuristic search syndromes d-algorithm lazy evaluation circuit simulation knowledge representation

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TESTABLE dESIGN WITH PLA MACROS

MICROPROCESSING AND MICROPROGRAMMING

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MICROPROCESSING ANd MICROPROGRAMMING 1985年第3期15卷 119-128页

作者： SOMENZI, F GAI, S MEZZALAMA, M PRINETTO, P POLITECN TORINO CTR ELABORAZ NUMERALE SEGNALI DIPARTIMENTO AUTOMAT & INFORMAT I-10128 TURIN ITALY SGS ATES COMPONENTI ELETTR CENT R&D AGRATE BRIANZA MILANO ITALY

The complexity of VLSI systems forces toward structured approaches to reduce both design time and test generation effort. PLA's and scan path have been widely reported to be efficient avenues of attack. In this paper an easily testable structure and related strategies are presented. Circuits are assumed to be based on the interconnection of combinatorial macros, mostly implemented by PLA's; tests are generated locally and then expressed in terms of primary inputs and outputs using a topological approach as general strategy and algebraic techniques for the propagation of signals through macros. Propagation is dealt with by new algorithms. As the problem of test generation is NP-hard, a set of heuristics is introduced to keep the amount of computation reasonable.

关键词： Automated test pattern generation design for testability Controllability Observability d-algorithm Boolean differences LSSd Structured design

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An automatic test generation system for illiac iv logic boards

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IEEE Transactions on Computers 1972年第9期C-21卷 1015-1017页

作者： Agrawal, Vishwani d. EG&G. Inc. Albuquerque N. 87106 United States Automation Technology Inc. Champaign ILL. United States

A test generation system, developed for the logic boards of the Illiac IV computer, is described. The system combines the test generation by random patterns and the d-algorithm. Some results are given to illustrate th... 详细信息

关键词： d-algorithm diagnosis fault diagnosis off-line computer random test generation test generation

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A Heuristic algorithm for the Testing of Asynchronous Circuits

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IEEE Transactions on Computers 1971年第6期C-20卷 639-647页

作者： Putzolu, Gianfranco R. Roth, J. Paul IBM Thomas J. Watson Research Center Yorktown Heights N.Y. 10598 United States

This paper describes an algorithm for the computation of tests to detect failures in asynchronous sequential logic circuits. It is based upon an extension of the d-algorithm [1]. discussion of experience with a progra... 详细信息

关键词： Circuit testing d-algorithm diagnosis LSI simulation test generation

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