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Assessment of vertical shifted carrier schemes for sinusoidal pulsewidth modulation

JOURNAL OF POWER ELECTRONICS 2024年第11期24卷 1719-1730页

作者： Kadiyala, Bhavana Paramasivan, Muthukumar Bensraj, R. Annamalai Univ Dept Elect Engn Annamalai Nagar Chidambaram 608002 Tamil Nadu India Saveetha Inst Med & Tech Sci Saveetha Sch Engn Dept Elect & Elect Engn Chennai Tamil Nadu India

The carrier modulated sinusoidal pulsewidth modulation scheme has been acknowledged for its fundamental fortification and harmonic reduction in DC-AC conversion. This study is focused on how to get a variable output voltage with the least harmonics by changing the amplitude of the carrier wave vertically instead of modulating the reference wave (conventional SPWM). This paper proposes four control schemes for achieving the maximum fundamental voltage in a three phase voltage source inverter. The four schemes are single edge carrier shifted with (i) fixed reference and (ii) variable reference, and double edge carrier shifted with (iii) fixed reference and (iv) variable reference. In addition, the reverse modulation index and mutual modulation index are introduced as new control variables for examination. These schemes are simulated with a three phase inverter and the performance is compared with conventional sinusoidal pulsewidth modulation using MATLAB R2021. The amplitude of the fundamental voltage and the corresponding THD are reported. Digital implementations of the proposed schemes are premeditated by using VHDL language and ModelSim. The validity of the proposed schemes is experimentally investigated through a laboratory prototype of a three phase inverter module incorporated with an FPGA Spartan 6 device. This prototype is tested with a three phase induction motor as the load. The fundamental voltage and THD for the existing and proposed schemes are reported.

关键词： Reverse modulation index Mutual modulation index Voltage source inverter Pulsewidth modulation field-programmable gate array

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Complexity Reduction by Using QR-Based Scheme in Computing Capacity for Optimal Transmission

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WIRELESS PERSONAL COMMUNICATIONS 2011年第2期58卷 391-405页

作者： Pan, Chien-Hung Natl Chiao Tung Univ Dept Commun Engn Hsinchu 300 Taiwan

Multiple-input-multiple-output (MIMO) technique is often employed to increase capacity in comparing to systems with single antenna. However, the computational complexity in evaluating channel capacity or transmission rate (data rate) grows proportionally to the number of employed antennas at both ends of the wireless link. Recently, the QR decomposition (QRD) based detection schemes have emerged as a low-complexity solution. After conducting QRD on a full channel matrix that results in a triangular matrix, we claim that computational complexity can be simplified by the following ways. First, to simplify channel capacity calculation, we prove that eigenvalues of the full channel matrix multiplication equals eigenvalues of the triangular channel matrix multiplication. Second, to simplify the calculation of the optimal transmission rate constrained constellation, we propose a simplistic multiplication of the resulted simple triangular matrix and a transmitted signal vector. Then, we also propose a modified mutual information calculation (MMIC) to achieve a quite low-complexity via the divided calculation. By using computer simulation and field- programmable gate array (FPGA) implementation, simulation results show that the proposed QRD-based schemes are capable of achieving conventional performance, but at a low-complexity level.

关键词： Multiple-input multiple-output Channel capacity QR decomposition Eigenvalues Mutual information field-programmable gate array

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Acceleration techniques and evaluation on multi-core CPU, GPU and FPGA for image processing and super-resolution

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JOURNAL OF REAL-TIME IMAGE PROCESSING 2019年第4期16卷 1207-1234页

作者： Georgis, Georgios Lentaris, George Reisis, Dionysios Natl & Kapodistrian Univ Athens Dept Phys Elect Lab Athens Greece

Super-resolution (SR) techniques constitute a key element in image applications, which need high-resolution reconstruction, while in the worst case, only a single low-resolution observation is available. SR techniques involve computationally demanding processes, and thus, researchers are currently focusing on SR performance acceleration. Aiming at improving the SR performance, the current paper builds up on the characteristics of the L-SEABI SR method to introduce parallelization techniques for GPUs and FPGAs. The proposed techniques accelerate GPU reconstruction of ultra-high definition content, by achieving three (3x) times faster than the real-time performance on mid-range and previous generation devices and at least nine times (9x) faster than the real-time performance on high-end GPUs. The FPGA design leads to a scalable architecture performing four (4x) times faster than the real-time on low-end Xilinx Virtex 5 devices and 69 times (69x) faster than the real-time on the Virtex 2000t. Moreover, we confirm the benefits of the proposed acceleration techniques by employing them on a different category of image processing algorithms: on window-based disparity functions, for which the proposed GPU technique shows an improvement over the CPU performance ranging from 14 times (14x) to 64 times (64x), while the proposed FPGA architecture provides 29x acceleration.

关键词： Real-time image processing Graphics processing unit field-programmable gate array Super-resolution Comparative power-performance evaluation

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Real-Time FPGA Investigation of Potential FEC Schemes for 800G-ZR/ZR+ Forward Error Correction

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JOURNAL OF LIGHTWAVE TECHNOLOGY 2023年第3期41卷 926-933页

作者： Wang, Weiming Long, Zhijun Qian, Weifeng Tao, Kai Wei, Zitao Zhang, Shihua Feng, Zhenhua Xia, Yan Chen, Yong ZTE Corp State Key Lab Mobile Network & Mobile Multimedia T Shenzhen 518055 Peoples R China ZTE Corp Wuhan 430223 Peoples R China

Forward error correction (FEC) performance down to 1e-15 bit error rate (BER) of a open FEC code (OFEC), which was recently proposed for the 800G inter-data center interconnect (DCI) standard, is verified with a 100-piece-FPGA implementation at a record 400-Gbps throughput. Besides the OFEC, we also investigate the cons and pros of the concatenated staircase and Hamming code (CFEC) and multilevel codes (MLC) of a concatenated Low-Density Parity-Check (LDPC) and Turbo Product Code (TPC), which are the candidate schemes for the 800G-ZR FEC. The OFEC performance as a function of decoding iterations of Soft-in Soft-out (SISO) and Hard-in Hard-out (HIHO) is investigated, and FPGA emulations reveal the existence of an error flare of the OFEC with two SISO iterations and an severe error floor with one HIHO iteration even with four SISO iterations. Further investigations on different combinations of SISO and HIHO iterations, revealed that three SISO and two HIHO iterations are the optimal choice. Based on this iteration configuration, we studied the methods that decreasing the test patterns (TP) of SISO decoder and the soft bits to reduce the implementation complexity. Then we proposed the simplified OFEC scheme for 800G-ZR application, providing 1.81e-2 pre-FEC BER threshold with half power dissipation of standard OFEC, achieving a trade-off between the error correction performance and power dissipation. Finally, we investigated the performance of performance enhanced OFEC with 24.3% overhead and 2.5e-2 pre-FEC threshold, and finally, FEC candidates for the 800G-ZR+ applications are studied, indicating that the OFEC and channel polarized multilevel coding (CP MLC) are the most promising schemes.

关键词： Forward error correction Codes Iterative decoding Standards Reliability Throughput Power dissipation 800G-ZR field-programmable gate array forward error correction optical fiber communication simplified OFEC

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Fast and accurate FPGA-based framework for processor architecture vulnerability analysis

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INTEGRATION-THE VLSI JOURNAL 2016年 53卷 14-26页

作者： Mahdiani, Hoda Safari, Saeed Salehi, Mostafa E. Univ Tehran Sch Elect & Comp Engn Tehran 14395515 Iran

This paper presents a fast, accurate, and flexible FPGA-based fault emulation platform, namely FARAVAM that can be exploited for AVF analysis in modern microprocessors. The proposed approach provides fault injection capabilities supporting automatic modification of post-synthesis net-lists and introduces a highly controllable and observable transient fault analysis environment. The presented vulnerability analysis platform using both exhaustive and random fault emulation approaches, provides useful information for identifying areas threatening reliability to make processors more fault tolerant. We applied our platform for extracting the best trade-offs between precision and speed up in vulnerability analysis of MIPS processor. The experimental results indicate that in addition to having high precision we obtain about seven orders of magnitude speed up in comparison with simulation based vulnerability analysis techniques. (C) 2015 Elsevier B.V. All rights reserved.

关键词： Architecture Vulnerability analysis Soft error Embedded processors Fault modeling and emulation field-programmable gate array

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A High-Resolution TDC-Based Board for a Fully Digital Trigger and Data Acquisition System in the NA62 Experiment at CERN

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2015年第3期62卷 1050-1055页

作者： Pedreschi, Elena Angelucci, Bruno Avanzini, Carlo Galeotti, Stefano Lamanna, Gianluca Magazzu, Guido Pinzino, Jacopo Piandani, Roberto Sozzi, Marco Spinella, Franco Venditti, Stefano Univ Pisa Dept Phys I-56100 Pisa Italy Natl Inst Nucl Res I-56127 Pisa Italy Natl Inst Nucl Phys I-56127 Pisa Italy CERN PH ESE FE Dept CH-1211 Geneva Switzerland

A time-to-digital converter-based system, to be used for most subdetectors in the high-flux rare-decay experiment NA62 at CERN SPS, was built as part of the NA62 fully digital trigger and data acquisition system in which the TDC Board (TDCB) and a general-purpose motherboard (TEL62) will play a fundamental role. While TDCBs, housing four high-performance time-to-digital converters (HPTDCs), measure hit times from subdetectors, the motherboard processes and stores them in a buffer, produces trigger primitives from different detectors, and extracts only data related to the lowest trigger level decision, once this is taken on the basis of the trigger primitives themselves. The features of the TDCB developed by the Pisa NA62 group are extensively discussed and performance data are presented in order to show its compliance with the experiment requirements.

关键词： Data acquisition field-programmable gate array trigger circuits

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Bit-parallel systolic multiplier over GF(2^m) for irreducible trinomials with ASIC and FPGA implementations

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IET CIRCUITS DEVICES & SYSTEMS 2018年第4期12卷 315-325页

作者： Mathe, Sudha Ellison Boppanal, Lakshmi Natl Inst Technol Dept Elect & Commun Engn Warangal 506004 Telangana India

Cryptography in digital world must offer integrity and confidentiality using cryptographic algorithms which mainly involve multiplication operation in finite fields. Various algorithms and architectures are proposed in the literature to obtain efficient finite field multiplications in both hardware and software. Here, a modified interleaved multiplication algorithm with reduced computational complexity is proposed based on a novel pre-computation (PC) technique to perform multiplication over for trinomials. Consequently, an m-bit systolic multiplier for trinomials (SMT) is designed by employing the proposed algorithm. Hardware and delay complexity analysis is performed and comparison of the proposed SMT structure with similar multipliers available in the literature is presented. The SMT structure achieves approximate to 28 and 17% improvement in hardware and area-delay product, respectively, for m=233 when compared with the best multiplier available in the literature. The functionality of the proposed SMT structure is also verified by implementing on field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) technologies. It can be observed from FPGA and ASIC implementation results that the proposed SMT structure shows improvement in area, power consumption, area-delay, and power-delay products when compared with similar multipliers available in the literature.

关键词： multiplying circuits application specific integrated circuits field programmable gate arrays cryptography computational complexity bit-parallel systolic multiplier irreducible trinomials ASIC FPGA cryptography cryptographic algorithms finite field multiplications modified interleaved multiplication algorithm computational complexity precomputation technique m-bit systolic multiplier delay complexity analysis SMT structure field-programmable gate array application specific integrated circuit power-delay products

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An Efficient VLSI Architecture for FastICA by Using the Algebraic Jacobi Method for EVD

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IEEE ACCESS 2021年 9卷 58287-58305页

作者： Sajjad, Muhammad Yusoff, Mohd Zuki Yahya, Norashikin Haider, Ali Shahbaz Univ Teknol PETRONAS Ctr Intelligent Signal & Imaging Res Seri Iskandar 32610 Perak Malaysia Oregon State Univ Dept Elect Engn & Comp Sci Corvallis OR 97331 USA

Blind source separation (BSS) is a problem that appears in many research fields. Fast Independent components analysis (FastICA) is one of the techniques to solve the problem. The researchers have verified the effectiveness of the technique through the offline analysis of the public datasets. The development of a real-time portable system involving such a computationally complex analysis requires an efficient hardware implementation of FastICA. A field programmable gate array (FPGA) and an application-specific integrated circuit (ASIC) are two promising hardware platforms to implement FastICA. This work proposes a new method, called ALgebraic Jacobi Method (ALJM), for performing eigenvalue decomposition (EVD) required for the implementation of FastICA. We use a simplification, a polynomial approximation, and the Newton-Raphson method for calculating the Jacobi rotation. In this way, we ensure hardware reusability between the EVD stage and the weight vector estimation (WVE) stage of FastICA which reduces the computational complexity and the power consumption, without compromising its computation speed. We evaluate the ALJM-based FastICA by performing BSS on the linear mixtures of the deterministic and the random signals and comparing the performance results with the existing methods. After verifying its functionality and numerical stability, we propose a scalable systolic processing array (SPA) for the ALJM-based FastICA and implement it on Spartan-6 FPGA. By comparing the existing implementations of FastICA, in terms of speed, area, and power, we conclude that the ALJM-based FastICA is one of the most efficient methods for prototyping and commercializing a real-time portable system comprising FastICA.

关键词： Jacobian matrices Hardware Real-time systems field programmable gate arrays Very large scale integration Computer architecture Convergence Application-specific integrated circuit ASIC blind source separation commercialization eigenvalue decomposition field-programmable gate array FastICA Fixed-point Designer independent components analysis Jacobi method VLSI

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Dual threshold input receiver FPGA-only signal digitization method for time-of-flight positron emission tomography

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BIOMEDICAL ENGINEERING LETTERS 2024年第4期14卷 847-858页

作者： Ko, Guen Bae Lee, Jae Sung Brightonix Imaging Inc Seoul 04782 South Korea Seoul Natl Univ Inst Radiat Med Med Res Ctr Seoul 03080 South Korea Seoul Natl Univ Coll Med Dept Nucl Med Seoul 03080 South Korea Seoul Natl Univ Coll Engn Interdisciplinary Program Bioengn Seoul 03080 South Korea

As silicon photomultiplier (SiPM)-based time-of-flight (TOF) positron emission tomography (PET) becomes popular, the need for sophisticated PET data acquisition (DAQ) systems is increasing. One promising solution to this challenge is the adoption of a field-programmable gate array (FPGA)-only signal digitization method. In this paper, we propose a new approach to efficiently implement an FPGA-only digitizer. We configured the input/output (IO) port of the FPGA to function as a dual-threshold voltage comparator through the use of simple passive circuitry and heterogeneous IO standards. This configuration overcomes the limitations of existing methods by allowing different threshold voltages for adjacent IO pins, effectively reducing routing complexity and lowering manufacturing costs. An FPGA-only digitizer was implemented by integrating the dual-threshold voltage comparator and FPGA-based time-to-digital converter. By combining the dual-threshold time-over-threshold (TOT) method and curve fitting, precise energy information could be obtained. The performance of the FPGA-only digitizer was assessed using a detector setup comprising a 3 x 3 x 20 mm3 LYSO scintillation crystal and a single pixel SiPM. Using the configured evaluation setup, an energy resolution of 12.5% and a time resolution of 146 +/- 9 ps were achieved for a 20 mm scintillation crystal. The dual-threshold TOT implemented using the proposed method showed consistent linearity across an energy range of 100 keV to 600 keV. The proposed method is well-suited for the development of cost-effective DAQ systems in highly integrated TOF PET systems.

关键词： Positron emission tomography field-programmable gate array Silicon photomultiplier Time-to-digital converter Time-over-threshold

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Hardware implementation and comparison of displacement retrieval algorithms for a laser diode-based optical feedback interferometric sensor

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2018年第4期26卷 1820-1832页

作者： Rehman, Ghazi Zabit, Usman Ullah, Muhammad Obaid Univ Engn & Technol Fac Elect & Elect Engn Dept Elect Engn Taxila Pakistan Natl Univ Sci & Technol Dept Elect Engn Islamabad Pakistan

Optical feedback interferometer (OFI) lasers, also called self-mixing (SM) lasers, have been widely explored over the last couple of decades due to their low cost, compactness, and self-aligned nature and they provide a very good solution for measurements of displacement, vibration, distance, velocity, etc. The SM effect takes place when a part of the laser beam is fed back to the active laser cavity after reflecting from the target. The reflected beam interferes with the emitted beam and hence the optical and spectral characteristics of the laser get changed. To retrieve the vibration or displacement signal of the target from the SM signal, different postprocessing algorithms have been proposed, such as the phase unwrapping method (PUM). The first step of the PUM leads to the coarse estimation of the laser phase and the final step is an iterative joint estimation of 2 parameters, namely laser coupling coefficient C and linewidth enhancement factor alpha. To make this algorithm applicable for real-time measurements, parallel joint estimation for a wide range of C and alpha values needs to be done. In this research, 3 algorithms, namely PUM, direct fringe unwrapping (DFU), and improved DFU (IDFU) were tested for FPGA implementation by using Verilog HDL (hardware description language) so that more precise and real-time vibration and displacement signals of targets could be extracted from the SM sensor in an embedded systems environment. These algorithms were developed using Verilog HDL for implementation on the Xilinx Spartan-3 Xcs400-FG320 development board. Our designed IDFU algorithm performed 0:492 times better than the parallel PUM algorithm in maximum clock frequency and 1:53 and 1:21 times better than the PUM in slice registers and LUT utilization of hardware resources, respectively. The designed DFU algorithm can operate 1:355 times better than IDFU in maximum clock frequency and 25:34 and 14:25 times better than IDFU in slice registers and LUT utilization of

关键词： Self-mixing laser sensors real time phase unwrapping method direct fringe unwrapping improved direct fringe unwrapping field-programmable gate array

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