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IEEE 73rd Electronic Components and Technology Conference (ECTC)

作者： Nadri, Souheil Tu, B-A. Clayton Herrault, Florian Sharifi, Hasan McCue, Jamin Khan, Abdullah Schwan, David Botticello, David Das, Sanjana Kuzmenko, Daniel Wong, Joel Phan, Vu Nguyen, Jason Wilt, Courtney HRL Labs LLC 3011 Malibu Canyon Rd Malibu CA 90265 USA Air Force Res Lab 2241 Avionics Cir Wright Patterson AFB OH 45433 USA Cadence Design Syst Inc 2655 Seely Ave San Jose CA 95134 USA

ISBN: (纸本)9798350334982

This paper describes the initial demonstration of a fan-out wafer-level package for high-density input/output (IO) digital CMOS chips using a silicon interposer with an embedded electroplated copper heat spreader. The package uses a redistribution layer (RDL) first chip-last approach featuring multi-layer interconnects that accommodate a minimum chip IO pitch of 10 mu m (30 mu m demonstrated). The integrated heat spreader simultaneously addresses fine- pitch chip integration, electrical shielding, and thermal management. The process development steps and challenges are discussed, and preliminary electrical results of passive test structures are presented showing > 95% DC connectivity. The paper also presents the development of a process design kit (PDK) in the Cadence Virtuoso environment for this technology and its application in shortening design time, preventing design rule violations, and extracting RC package parasitics.

关键词： fan-out wafer-level package fine-pitch CMOS chips silicon interposer electroplated copper heat spreader process design kit

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Investigation on the Effects of Interconnect RC in 3nm Technology Node Using Path-Finding process design kit

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IEEE ACCESS 2022年 10卷 80695-80702页

作者： Lee, Yeji Jang, Wonyeong Kwon, Kyungbae Park, Jihun Yoo, Changhyun Chang, Jeesoo Jeon, Jongwook Konkuk Univ Dept Elect & Elect Engn Seoul 05029 South Korea Samsung Elect Innovat Ctr Hwasung Si 16677 Gyeonggi Do South Korea

With the continuous development of front-end-of-line (FEOL) technology, the development of interconnection processes at nanoscale process nodes is becoming important. We conducted a post-layout circuit simulation to consider the effect of parasitic R and C components of middle-of-Line (MOL) and back-end-of-line (BEOL) on the circuit performance. We constructed a process design kit (PDK) for path-finding to analyze the circuit layout in a 3nm technology node based on gate-all-around FET (GAA-FET). It consists of the spice model library that satisfies the 3nm power performance area (PPA) target, and the layout versus schematic (LVS), parasitic extraction (PEX) model that checks whether the layout and schematic match, extracts the RC values in the FEOL MOL and BEOL areas. Subsequently, the effect of the interconnection on complex logic circuits (RO, full adder) was confirmed using PDK. As a result of quantifying the effects of FEOL, MOL, and BEOL on the circuit, circuit degradation due to the RC of MOL and BEOL accounts for more than 60%. Furthermore, we introduced the air spacer process as a way to improve the circuit performance by reducing the C-MOL owing to the reduction in the dielectric constant of the spacer. When an air spacer is introduced, based on 9-stages FO1 INV RO with k = 7 at V-DD = 0.7V, under iso-speed condition, the active power decreases by 30%, 35% when k is 3.3, 1.65, respectively. Under iso-power condition, frequency increases by 9%, 11% when k is 3.3, 1.65, respectively. And based on full adder with k = 7 at V-DD = 0.7V, Under iso-speed conditions, the active power decreases by 47%, 58% when k is 3.3, 1.65, respectively. Under iso-power conditions, the delay decreases by 14%, 20% when k is 3.3, 1.65, respectively. PDP decreases by 22%, 32% when k is 3.3, 1.65, respectively. EDP decreases by 31%, 44% when k is 3.3, 1.65, respectively. In conclusion, in this work, we provide a guide for determining the BEOL load and developing an improved wiring p

关键词： Integrated circuit modeling Wiring Resistance Layout Three-dimensional displays Metals Logic gates Gate-all-around FET process design kit parasitic extraction benchmark air spacer

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Compact Modeling of Key Passive Silicon Photonic Components for a process design kit

Compact Modeling of Key Passive Silicon Photonic Components ...

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Annual Conference of the IEEE-Photonics-Society (IPC)

作者： Hossain, Mohammad Jobayer Dikshit, Amit Wallner, Jin Uddin, Mohammad Rakib Timalsina, Yukta Carpenter, Lewis G. Mann, Javery Fahrenkopf, Nicholas M. Harame, David L. Amer Inst Mfg Integrated Photon AIM Photon Albany NY 12203 USA Res Fdn State Univ New York Albany NY 12203 USA

process design kits (PDKs) enable the rapid design of photonic integrated circuits with predictable performance. Compact modeling is an important step in developing PDKs. We explain the methodologies developed for cre... 详细信息

ISBN: (纸本)9798350347227

关键词： compact model process design kit waveguide directional coupler crossing ring resonator grating coupler

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SUNY POLY Foundry process design kit: A Unique design Enablement Platform for Photonic Integrated Circuit design 17

SUNY POLY Foundry Process Design Kit: A Unique Design Enable...

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Conference on Silicon Photonics XVII Part of SPIE Photonics West OPTO Conference

作者： Dikshit, Amit Wallner, Jin Bergman, Barton Uddin, M. Rakib Carpenter, Lewis G. Timalsina, Yukta P. Begovic, Amir Cotter, Chandra Casline Fahrenkopf, Nicholas M. Baiocco, Christopher Leake, Gerald, Jr. Harame, David L. SUNY Albany Res Fdn Polytech Inst Albany NY 12203 USA Rensselaer Polytech Inst Dept Elect Comp & Syst Engn Troy NY 12180 USA

ISBN: (纸本)9781510648845;9781510648838

A novel process design kit (PDK) offering providing seamless access to the Albany NanoTech Complex's 300mm foundry with a mission to promote silicon photonics technology is demonstrated. Unlike traditional pure-play foundries, we have developed a framework that allows our PDKs to contain libraries developed by internal and external domain experts. In addition to integrated Electronic Photonic design Automation (EPDA) platforms, our PDK is also released in an alternate PIC design flow that the lowers the cost barrier for organizations. Further, our PDKs target a broad application space that includes telecom as well emerging areas such as sensors and quantum photonics - all with the ability for onboard light sources. A PDK from American Institute of Manufacturing (AIM Photonics) will be discussed that demonstrates these features.

关键词： Silicon Photonics process design kit Compact Models Layout Schematic Integrated photonic devices

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process design kits Management for Multiple processes applied to Silicon Technologies 9

Process Design Kits Management for Multiple Processes applie...

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IEEE 9th Electronics System-Integration Technology Conference (ESTC)

作者： Aubry, Yves Jehannin, Florent Remond, Matthieu Murata Integrated Pass Solut R&D Caen France

ISBN: (数字)9781665489478

ISBN: (纸本)9781665489478

Semi-conductor technologies are evolving fast and have an increasing number of applications in a wide range of domains and markets. Computer Aided design (CAD) tools need to be adapted to these new technologies. There are different CAD software available on the global market. These software programs all have unique features adapted to the needs of companies but they include the same modules: layout, design, simulation and verification. These software programs need to be fed with process design kits (PDK) to allow designers to meet manufacturing constraints and run simulations. PDKs are generally specifically created for a particular technology. In this paper, we show a way to manage and create multiple PDKs for different types of technology and software programs. To that end, we use a database containing technology and software independent information. We apply PDK management to silicon 3D capacitors technologies and related components.

关键词： process design kit PDK Management Silicon 3D capacitors

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Advanced Quality Assurance Platform for Robust process design kits 31st

Advanced Quality Assurance Platform for Robust Process Desig...

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31st International Conference on Very Large Scale Integration

作者： Datsuk, Anton Ostrovskyy, Philip Vater, Frank Wieden, Christian IHP Leibniz Inst Innovat Mikroelekt Technol Pk 25 D-15236 Frankfurt Oder Germany

ISBN: (纸本)9783031709494;9783031709470;9783031709463

process design kits (PDKs) and their robustness verification are pivotal to a semiconductor foundry's growth and customer retention. This paper presents an extended version of our automated PDK quality assurance (QA) platform, initially introduced to maintain production-quality PDKs deployable at any time. The platform utilizes continuous integration and continuous delivery tools to detect and resolve problems early, significantly reducing the time required for pre-release PDK verification. We have embedded this QA platform into the PDK verification flow for 0.13 mu m and 0.25 mu m SiGe BiCMOS technologies, ensuring reliable on-demand PDK releases. Additionally, we extend our discussion to include the results viewer application that enhances identification and organization of the issues across various PDKs, further improving verification efficiency. This paper also introduces a new analysis of the trend in PDK issues reported by customers, illustrating the platform's effectiveness in quality assurance and optimization of the PDK development process for semiconductor technologies. The enhanced features and insights detailed in this paper reinforce our approach and highlight significant improvements in interoperable PDK verification, utilizing previously released PDKs as benchmarks.

关键词： process design kit quality assurance continuous integration continuous delivery interoperable PDK

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Towards Robust process design kits with a Scalable DevOps Quality Assurance Platform 31

Towards Robust Process Design Kits with a Scalable DevOps Qu...

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31st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

作者： Datsuk, A. Ostrovskyy, P. Vater, F. Wieden, C. IHP Leibniz Inst Innovat Mikroelekt Technol Pk 25 D-15236 Frankfurt Oder Germany

ISBN: (纸本)9798350325997

process design kits (PDK) and their robustness verification is pivotal to a semiconductor foundry's growth and customer retention. This paper presents an automated PDK quality assurance (QA) platform that is based on a continuous integration and continuous delivery tool. The tool helps to keep a PDK at the production quality level guaranteeing its deployment at any time. The introduced methodology allows detecting and resolving problems at earlier stages, while significantly reducing the time required for a pre-release PDK verification. The QA platform was embedded into a PDK verification flow for 0.13 mu m and 0.25 mu m SiGe BiCMOS technologies resulting in reliable PDK releases on demand. Moreover, we utilize the proposed PDK QA platform to perform verification of the interoperable PDK while using a formerly released PDK as a reference.

关键词： process design kit quality assurance continuous integration continuous delivery interoperable PDK

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Study on the Circuit Performance of Various Interconnect Metal Materials in the Latest process Nodes

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JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2023年第4期23卷 215-227页

作者： Choi, Moonjeong Park, Juhwan Choi, Seoungyeol Kwon, Kyungbae Lee, Yeji Jang, Wonyeong Jeon, Jongwook Konkuk Univ Dept Elect & Elect Engn Seoul 05029 South Korea Sungkyunkwan Univ Sch Elect & Elect Engn Suwon 16419 South Korea

In this work, circuit-level benchmarks were performed on Copper(Cu), Tungsten(W), Cobalt(Co), Ruthenium(Ru), and Doped-multilayer-graphene (DMLG), which are various metallic material options applicable to the wire process at the late semiconductor process nodes. For the transistor, a multi-nanosheet field-effect-transistor (mNS-FET) with gate-all-around (GAA) technology was used, and the power and performance characteristics of the inverter ring oscillator circuit were analyzed assuming a 3 nm process node. In addition, various wire metal options for circuit layout were evaluated by varying fan-out number and wire length. As a result, the speed is fastest for Co and the speed reduction is smallest for DMLG in FO1 50CPP.

关键词： Gate-all-around FET process design kit parasitic extraction benchmark interconnect

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Invited: Modeling and design Methodology for Backside Integration of Voltage Converters 25

Invited: Modeling and Design Methodology for Backside Integr...

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34th International Symposium on Physical design-ISPD

作者： Rahman, Amaan Yang, Hang Hao, Cong Lim, Sung Kyu Georgia Inst Technol Atlanta GA 30332 USA

ISBN: (纸本)9798400712937

As technology scales down, backside power delivery networks (BS-PDNs) are increasingly adopted to address frontside parasitics, power density, and IR-drop challenges. However, conventional BS-PDN architectures struggle with off-chip IR-drop issues caused by package-level parasitics. We introduce the first fully integrated backside voltage regulator (BS-IVR) to reduce off-chip circuitry overhead, and improve load regulation and on-chip power integrity. BS-IVR utilizes back-end-of-line compatible amorphous tungstendoped indium oxide transistors for backside integration and our comprehensive backside PDK for design and verification. We developed an end-to-end EDA flow for BS-IVR on-chip integration and power integrity analysis. Optimizing the BS-IVR for on-chip integration achieves a compact IVR footprint of 0.0142 mm(2) with a power density of 3.02 W/mm(2) and efficiency of 60%. On-chip dynamic VDD IR-drop is further reduced by 46.06%.

关键词： Integrated voltage regulators backside technology 3D monolithic IC physical design process design kit

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Porting OpenRAM generator to an OTFT process 6

Porting OpenRAM generator to an OTFT process

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2024 IEEE International Flexible Electronics Technology Conference

作者： Herrera-Sanchez, Pablo Rezaee, Ashkan Saiz, Joaquin Castells-Rufas, David Ogier, Simon Casanova, Raimon Carrabina, Jordi Autonomous Univ Barcelona Microelect Dept Bellaterra Spain Flexi SL R&D Dept Sant Cugat Del Valles Spain Smartkem Ltd R&D Dept Sedgefield England

ISBN: (纸本)9798331529475;9798331529468

Memories are essential components for building flexible organic integrated microsystems for Smart Sensors. This work presents the steps to build a parameterizable SRAM memory generator for the 6-layer OTFT PMOS process from Smartkem mapping the existing tools of the open-source OpenRAM framework. Python coding of structures allows a quick porting to similar technologies or to other regular structures (such as ROM or PLAs).

关键词： Flexible circuit elements SRAM OTFT circuit design process design kit open-source EDA tools

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